Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-01
2006-08-01
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07086023
ABSTRACT:
The present invention is a system and method for determining criticality probability of each node, edge and path of the timing graph of a digital circuit in the presence of delay variations. The delay of each gate or wire is assumed to consist of a nominal portion, a correlated random portion that is parameterized by each of the sources of variation and an independent random portion. Correlations are taken into account. Both early mode and late mode timing are included; both combinational and sequential circuits are handled; static CMOS as well as dynamic logic families are accommodated. The criticality determination complexity is linear in the size of the graph and the number of sources of variation. The invention includes a method for efficiently enumerating the critical path(s) that is/are most likely to be critical.
REFERENCES:
Ababei et al., “Timing Minimization by Statistical Timing hMetis-based Partitioning”, Jan. 2003, IEEE 16thInternational Conference on VLSI Design, Paper Digest pp. 56-63.
Statistical Timing of Parametric Yield Prediction of Digital Integrated Circuits, by J.A.G. Jess, K. Kalafala, S.R. Naidu, R.H.J.M. Otten, C. Visweswariah, pp. 932-937, Design Automation Conference 2003.
Fast Statistical Timing Analysis By Probabilistic Event Propagation, by Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, and Angela Krstic, pp. 661-666, Design Automation Conference 2001.
Explicit Computation of Performance as a Function of Process Variation by Lou Scheffer, TAU '02, pp. 1-8.
Timing Yield Estimation from Static Timing Analysis, by Anne Gattiker, Sani Nassif, Rashmi Dinakar, and Chris Long, pp. 437-442, International Symposium on Quality Electronic Design, 2001.
Hoffman Warnick & D'Alessandro LLC
Karra Satheesh K.
Lin Sun James
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