Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
Reexamination Certificate
2011-07-19
2011-07-19
Alrobaye, Idriss N (Department: 2183)
Electrical computers and digital processing systems: processing
Instruction issuing
Simultaneous issuance of multiple instructions
C712S221000, C712S214000, C712S216000
Reexamination Certificate
active
07984270
ABSTRACT:
The present invention provides a system and method for prioritizing arithmetic instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in a delayed manner relative to each other. The system further includes circuitry configured to: (1) receive an issue group of instructions; (2) determine if at least one arithmetic instruction is in the issue group, if so scheduling the least one arithmetic instruction in a one of the plurality of execution pipelines based upon a first prioritization scheme; (3) determine if there is an issue conflict for one of the plurality of execution pipelines and resolving the issue conflict by scheduling the at least one arithmetic instruction in a different execution pipeline; (4) schedule execution of the issue group of instructions in the cascaded delayed execution pipeline unit.
REFERENCES:
patent: 5430851 (1995-07-01), Hirata et al.
patent: 5471593 (1995-11-01), Branigin
patent: 5561774 (1996-10-01), Aikawa et al.
patent: 5627982 (1997-05-01), Hirata et al.
patent: 5640588 (1997-06-01), Vegesna et al.
patent: 5768610 (1998-06-01), Pflum
patent: 5802386 (1998-09-01), Kahle et al.
patent: 5922065 (1999-07-01), Hull et al.
patent: 5948098 (1999-09-01), Leung et al.
patent: 6018798 (2000-01-01), Witt et al.
patent: 6154829 (2000-11-01), Mino et al.
patent: 6260190 (2001-07-01), Ju
patent: 6289445 (2001-09-01), Ekner
patent: 6338136 (2002-01-01), Col et al.
patent: 6496924 (2002-12-01), Sakamoto
patent: 6618802 (2003-09-01), Arnold et al.
patent: 6862677 (2005-03-01), Stravers
patent: 6912648 (2005-06-01), Hammarlund et al.
patent: 7222227 (2007-05-01), Katayama et al.
patent: 7281119 (2007-10-01), Cofler et al.
patent: 7308562 (2007-12-01), Haugh
patent: 7363467 (2008-04-01), Vajapeyam et al.
patent: 2002/0169942 (2002-11-01), Sugimoto
patent: 2003/0126408 (2003-07-01), Vajapeyam et al.
patent: 2003/0131030 (2003-07-01), Sebot et al.
patent: 2003/0177338 (2003-09-01), Luick
patent: 2003/0182534 (2003-09-01), Harthcock
patent: 2004/0059891 (2004-03-01), Luick
patent: 2004/0073753 (2004-04-01), Luick
patent: 2004/0083468 (2004-04-01), Ogawa et al.
patent: 2004/0103336 (2004-05-01), Flores et al.
patent: 2004/0154006 (2004-08-01), Heishi et al.
patent: 2004/0181651 (2004-09-01), Sugumar et al.
patent: 2005/0114856 (2005-05-01), Eickemeyer et al.
patent: 2005/0166038 (2005-07-01), Wang et al.
patent: 2006/0090061 (2006-04-01), Akkary et al.
patent: 2006/0101241 (2006-05-01), Curran et al.
patent: 2006/0168583 (2006-07-01), Basso et al.
patent: 2006/0179280 (2006-08-01), Jensen et al.
patent: 2007/0011434 (2007-01-01), Luick
patent: 2007/0143581 (2007-06-01), Mansell
patent: 2007/0186073 (2007-08-01), Luick
patent: 2007/0186080 (2007-08-01), Luick
patent: 2007/0288725 (2007-12-01), Luick
patent: 2008/0162890 (2008-07-01), Sathaye
patent: 2009/0031120 (2009-01-01), Vaden
patent: 2009/0210665 (2009-08-01), Bradford et al.
patent: 2009/0210666 (2009-08-01), Luick
patent: 2009/0210667 (2009-08-01), Luick
patent: 2009/0210668 (2009-08-01), Luick
patent: 2009/0210669 (2009-08-01), Luick
patent: 2009/0210671 (2009-08-01), Luick
patent: 2009/0210672 (2009-08-01), Luick
patent: 2009/0210673 (2009-08-01), Luick
patent: 2009/0210674 (2009-08-01), Luick
patent: 2009/0210676 (2009-08-01), Luick
patent: 2009/0210677 (2009-08-01), Luick
patent: 2009/0240919 (2009-09-01), Alexander et al.
U.S. Appl. No. 12/033,100 Non-Final Office Action dated Apr. 30, 2010.
U.S. Appl. No. 12/033,111 Non-Final Office Action dated May 3, 2010.
U.S. Appl. No. 12/033,140 Non-Final Office Action dated Apr. 28, 2010.
U.S. Appl. No. 12/033,034 Non-Final Office Action dated Jun. 1, 2010.
U.S. Appl. No. 12/033,038 Non-Final Office Action dated Jun. 1, 2010.
U.S. Appl. No. 12/033,043 Non-Final Office Action dated Jun. 1, 2010.
U.S. Appl. No. 12/033,045 Non-Final Office Action dated Jun. 4, 2010.
U.S. Appl. No. 12/033,052 Notice of Allowance dated Aug. 25, 2010.
Jianghua Wan & Shuming Chen, “Reducing Conflicts in SMT VLIW Processor for Higher Throughput,” Dec. 2005, 7 pgs; Embedded Software and Systems, Second International Conference, IEEE.
U.S. Appl. No. 12/033,034; Final Office Action; filed Feb. 19, 2008; Date Mailed: Oct. 25, 2010.
U.S. Appl. No. 12/033,038; Final Office Action; filed Feb. 19, 2008; Date Mailed: Oct. 25, 2010.
U.S. Appl. No. 12/033,043; Final Office Action; filed Feb. 19, 2008; Date Mailed: Oct. 25, 2010.
U.S. Appl. No. 12/033,045; Final Office Action; filed Feb. 19, 2008; Date Mailed: Oct. 25, 2010.
U.S. Appl. No. 12/033,085; Notice of Allowance; Date Mailed: Sep. 22, 2010.
U.S. Appl. No. 12/033,100; Final Office Action; Date Mailed: Sep. 14, 2010.
U.S. Appl. No. 12/033,111; Final Office Action; filed Feb. 19, 2008; Date Mailed: Oct. 13, 2010.
U.S. Appl. No. 12/033,122; Notice of Allowance; Date Mailed: Sep. 20, 2010.
U.S. Appl. No. 12/033,127; Notice of Allowance; Date Mailed: Sep. 1, 2010.
U.S. Appl. No. 12/033,140; Final Office Action; Date Mailed: Sep. 2, 2010.
Alrobaye Idriss N
Cantor & Colburn LLP
International Business Machines - Corporation
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