Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-07-01
2001-07-10
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S163000, C711S167000
Reexamination Certificate
active
06260116
ABSTRACT:
BACKGROUND OF THE INVENTION
In processor designs which use a cache memory architecture, overall performance can be greatly improved by prefetching instructions from a bulk storage unit and placing then in a cache memory prior to the time the processor will be using them. This is easily accomplished with program instructions since they are sequential in nature. The sequential nature of program instructions allows a memory controller to prefetch a group of instructions and load them into a cache line based simply on the current instruction address. Prefetch mechanisms for data do not work very well since data, unlike program instructions, is generally not sequential in nature or arranged in the order the program will access it.
SUMMARY OF THE INVENTION
The invention contemplates a method and system for prefetching data from storage and storing the data in a cache memory for use by an executing program. The system includes means for detecting when a program has entered a processing loop and has completed at least one pass through the processing loop. At the completion of the at least one pass through the processing loop, means for determining the requirement for additional data and prefetching the required data, monitoring the operation of the program to detect termination of loop processing and terminating the prefetch of data from storage until the detection of a subsequent program loop.
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Davis Gordon Taylor
Marshall, IV Llewellyn Bradley
Ogilvie Clarence Rosser
Stabler Paul Colvin
Frisone John B.
International Business Machines - Corporation
Kim Matthew
Reid Scott W.
Tzeng Fred F.
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