Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-13
2004-11-30
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06826739
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to computer-aided circuit design systems and more particularly to an electrical rules checker system and method for placing substrate contacts into a datapath stack in an integrated circuit design.
2. Discussion of the Related Art
Integrated circuits (ICs) are electrical circuits comprising transistors, resistors, capacitors, and other components on a single semiconductor “chip” in which the components are interconnected to perform a variety of functions. Typical examples of ICs include, for example, microprocessors, programmable logic devices (PLDs), electrically erasable programmable read only memory (EEPROM) devices, random access memory (RAM) devices, operational amplifiers and voltage regulators. A circuit designer typically designs the IC by creating a circuit schematic indicating the electrical components and their interconnections. Often, designs are simulated by computer to verify functionality and to ensure that performance goals are satisfied.
In electrical device engineering, the design and analysis work involved in producing electronic devices is often performed using electronic computer-aided design (E-CAD) tools. As will be appreciated, electronic devices include analog, digital, mixed hardware, optical, electro-mechanical, and a variety of other electrical devices. The design and subsequent simulation of any circuit, very large scale integration (VLSI) chip, or other electrical device via E-CAD tools allows a curcuit to be thoroughly tested and often eliminates the need for building a prototype. Thus, today's sophisticated E-CAD tools may enable the circuit manufacturer to go directly to the manufacturing stage without having to perform costly, time consuming prototyping.
In order to perform the simulation and analysis of a hardware device, E-CAD tools utilize an electronic representation of the hardware device. A “netlist” is one common representation of a hardware device that includes the circuit. As will be appreciated by those skilled in the art of hardware device design, a “netlist” is a detailed circuit specification used by logic synthesizers, circuit simulators and other circuit design optimization tools. A netlist typically comprises a list of circuit components and the interconnections between those components.
The two forms of a netlist are the flat netlist and the hierarchical netlist. Often, a netlist will contain a number of circuit “modules” which are used repetitively throughout the larger circuit. A flat netlist will contain multiple copies of the circuit modules essentially containing no boundary differentiation between the circuit modules and other components in the device. By way of analogy, one graphical representation of a flat netlist is simply the complete schematic of the circuit device.
In contrast, a hierarchical netlist will only maintain one copy of a circuit module, which may be used in multiple locations. By way of analogy, one graphical representation of a hierarchical netlist would show the basic and/or non-repetitive devices in schematic form and the more complex and/or repetitive circuit modules would be represented by “black boxes.” As will be appreciated by those skilled in the art, a black box is a system or component where the inputs, outputs, and general function are known, but the contents of which are not shown. These “black box” representations, hereinafter called “modules,” will mask the complexities therein, typically showing only input/output ports.
An IC design can be represented at different levels of abstraction, such as at the register-transfer level (RTL) and the at logic level, using a hardware description language (HDL). VHDL® and Verilog® are examples of HDL languages. At any abstraction level, an IC design is specified using behavioral or structural descriptions, or a mix of both. At the logical level, the behavioral description is specified using Boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells are, among others, full-adders, logic gates, latches, and flip flops.
Set forth above is some very basic information regarding integrated circuits and other circuit schematics that are represented in netlists. Systems are presently known that use the information provided in netlists to evaluate circuit timing and other related parameters. More specifically, systems are known that perform a timing analysis of circuits using netlist files. Although the operational specifics may vary from system to system, generally, such systems operate by identifying certain critical timing paths, then evaluating the circuit to determine whether timing violations may occur through the critical paths. As is known, timing specifications may be provided to such systems by way of a configuration file.
FIG. 1A
is a block diagram illustrating a prior art static timing analyzer system that illustrates the basic informational flow in such a system and that is generally denoted by reference numeral
2
. Specifically, one such system
2
is marketed under the name PathMill®.
FIG. 1
illustrates the informational flow in system
2
. At the center of the diagram is a static timing analyzer
10
, (i.e., the PathMill® program). Surrounding this block
10
are a number of other blocks that represent various input and output files and/or information.
More particularly, the static timing analyzer
10
may utilize a configuration file
12
, a file of timing models
14
, one or more netlist files
16
, a technology file
18
, and a parasitics file
20
, for various input information. In addition, the static timing analyzer
10
may generate a number of different output files or other output information, including a critical path report
22
, a runtime log file
24
, an error report
26
, a software interface file
28
, and a SPICE netlist
30
. When started, the static timing analyzer
10
first processes the input netlist file(s)
16
, the technology file
18
, and the configuration files
12
. The information from these files is subsequently used for performing path analyses. The function and operation of static timing analyzer
10
are generally well known, and therefore will not be discussed in detail herein.
While tools such as these are useful for the design verification process after layout, there are various shortcomings in the static timing analyzer
10
, and other similar products. These shortcomings include, but are not limited to, the ability to identify appropriate locations for and place substrate contacts in a datapath stack
50
as illustrated in FIG.
1
B. These substrate contacts are elements known in the art, and are needed to prevent latch-up of the circuitry.
Typically, the placing of substrate contacts in a datapath stack involves manually determining where the substrate contacts are needed and then adding them by hand. This manual addition of substrate contacts is currently extremely imprecise, time consuming, tedious and labor intensive and thus, few substrate contacts are placed manually. In addition, the manual addition of substrate contacts is very error prone due to the density and complexity of the datapath macros that are now incorporated into current integrated circuit technology. This lack of space between the datapath macros
51
is illustrated in FIG.
1
B. In particular, the lack of space is illustrated between datapath macro
51
B and
51
C and among datapath macros
51
D,
51
E and
51
F.
Consequently, there is a heretofore unaddressed need existing in the industry for a way to address the aforementioned deficiencies and inadequacy.
SUMMARY OF THE INVENTION
The present invention provides a substrate contact placement system and method for placing substrate contacts in a datapath stack.
Briefly described, in architecture, the substrate contact placement system can be implemented as follows. A first logic establishes a floorplan for a datapath stack containing a plurality of datapath macros in a netlist, and a second logic determines a placement
Agilent Technologie,s Inc.
Kik Phallaka
Thompson A. M.
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