Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
1998-12-16
2001-10-09
Hjerpe, Richard (Department: 2674)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C712S204000, C712S205000, C712S210000, C712S218000, C712S244000
Reexamination Certificate
active
06301654
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to the execution of out-of-order load and store instructions in a processor.
BACKGROUND INFORMATION
In order to increase the operating speed of microprocessors, architectures have been designed and implemented that allow for the out-of-order execution of instructions within the microprocessor. An advantage of out-of-order execution of instructions is that it allows load miss latencies to be hidden while useful work is being performed. However, traditionally, load and store instructions have not been executed out of order because of the very nature of their purpose. For example, if a store instruction is scheduled to be executed in program order prior to a load instruction, but the processor executes these two instructions out of order so that the load instruction is executed prior to the store instruction, and these two instructions are referring to the same memory space, there is a likelihood that the load instruction will load incorrect, or old, data since the store instruction was not permitted to complete prior to the load instruction.
Nevertheless, techniques have been implemented to attempt to execute load and store instructions out of order. However, such techniques have often required too many processor cycles to execute. As microprocessor speeds continually increase, there is a need in the art for an ability to execute in parallel such load and store instructions and to correct for such problems as described above in a more efficient and faster manner.
SUMMARY OF THE INVENTION
The present invention provides a mechanism to allow out-of-order load and store execution and a means to recover from problems which occur from such execution in an efficient manner.
The present invention addresses the foregoing need by tagging the load and store instructions and then maintaining entries in separate queues for the load and store instructions, in conformance with the assigned tags.
At instruction dispatch, each store instruction is assigned an STAG (store tag) and LTAG (load tag), where the STAG is incremented by a preceding store instruction (in program order) and the LTAG is incremented by preceding load instructions. Each load instruction is assigned an LTAG and STAG, where the LTAG is incremented by a preceding load instruction (in program order). Addresses are queued in a load reorder queue and a store reorder queue in position relative to their LTAG (STAG). Conflicts can then be detected since the relative program order is known at address generation time.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 5664215 (1997-09-01), Burgess et al.
patent: 5887161 (1999-03-01), Cheong et al.
patent: 5931957 (2000-08-01), Konigsburg et al.
Ronchetti Bruce Joseph
Shippy Dave
Thatcher Larry Edward
England Anthony V. S.
Hjerpe Richard
International Business Machines - Corporation
Kordzik Kelly K.
Monestime Mackly
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