System and method for performing reed-solomon encoding

Details System and method for performing reed-solomon encoding System and method for performing reed-solomon encoding

2011-01-25

2011-01-25

Rizk, Sam (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S752000, C714S758000

Reexamination Certificate

active

07877672

ABSTRACT:
An embodiment of the present invention provides a system for implementing a Reed-Solomon computation of parity bytes of a codeword, including an accumulator and a logic circuit. The accumulator is configured to hold a plurality of bits. In an embodiment, each bit held in the accumulator initially corresponds to a bit associated with a data byte of the codeword. In another embodiment, each bit held in the accumulator initially correspond to a fixed value. The logic circuit is configured to iteratively compute a new bit for each bit held in the accumulator. After a last iteration of the computation, the bits held in the accumulator correspond to the parity bytes, wherein for each bit held in the accumulator each iteration of the computation comprises computing an exclusive-OR of a fixed subset of bits held in the accumulator. In an embodiment, the exclusive-OR is computed for the fixed subset of bits held in the accumulator and an input bit of the codeword.

REFERENCES:
patent: 6353909 (2002-03-01), Amrany et al.
patent: 2008/0126908 (2008-05-01), Lin
Stephen B. Wicker and Vijay K. Bhargava, An Introduction to Reed-Solomon Codes, in Reed-Solomon Codes and Their Applications, 1-16, (Stephen B. Wicker and Vijay K. Bhargava eds.), New York, NY, 1994.

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