Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-09-29
2002-07-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C430S005000
Reexamination Certificate
active
06425117
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the area of electronic design automation (EDA), and more particularly to optical proximity correction of sub-micron mask designs.
2. Description of Background Art
A fabrication mask or reticle is used when fabricating a semiconductor device. Such a mask has a light-transparent portion (e.g., glass) and a light-shielding portion (e.g., chromium) that define a circuit pattern to be exposed on a wafer. Such patterns may define diffusion regions or field oxidation regions provided on a substrate. They may also define gate electrode patterns at a polysilicon level or a metal line patterns at any metallization layer of a chip. The mask and reticle must have a precisely defined circuit pattern. Photolithography is a process used for patterning semiconductor wafers during the manufacture of integrated circuits, such as application specific integrated circuits (ASICs).
The reticle is placed between a radiation source producing radiation of a pre-selected wavelength and a focusing lens which may form part of a “stepper” apparatus. Placed beneath the stepper is a resist covered silicon wafer. When the radiation from the radiation source is directed onto the reticle, that fraction of the radiation passing through the glass projects onto the resist covered silicon wafer. In this manner, an image of the reticle is transferred to the resist. For further information on IC fabrication and resist development methods, reference may be made to a book entitled
Integrated Circuit Fabrication Technology
by David J. Elliott, McGraw Hill, 1989.
Light passing by the edge of a reticle pattern feature (e.g., the boundary between a chromium coated region and a transparent region) will be diffracted, so that rather than producing a very sharp image of the feature edge, some radiation diffracts beyond the intended image boundary and into the dark regions. Hence feature shapes and sizes deviate somewhat from the intended design. For ultraviolet radiation in common use today, the intensity of the diffracted radiation drops off quickly over a fraction of a micron, so the affect does not prove particularly problematic when devices have dimensions on the order of 1 micrometer. However, as device dimensions have shrunk to the submicron domain, diffraction effects can no longer be ignored.
The diffraction errors can be compensated for by increasing the thickness of various critical features on the pattern. For example, increasing the width of a line on the pattern will reduce the diffraction effects. Unfortunately, this defeats the purposes of using small critical dimension features; greater logic density and improved speed.
FIG. 1A
shows a hypothetical reticle
100
corresponding to an IC layout pattern. For simplicity, the IC pattern consists of three rectangular design features. A clear reticle glass
110
allows radiation to project onto a resist covered silicon wafer. Three rectangular chromium regions
102
,
104
and
106
on reticle glass
110
block radiation to generate an image corresponding to intended IC design features.
FIG. 1B
illustrates how diffraction and scattering affect an illumination pattern produced by radiation passing through reticle
100
and onto a section of silicon substrate
120
. As shown, the illumination pattern contains an illuminated region
128
and three dark regions
122
,
124
, and
126
corresponding to chromium regions
102
,
104
, and
106
on reticle
100
. The illuminated pattern exhibits considerable distortion, with dark regions
122
,
124
, and
126
having their corners rounded and their feature Widths reduced. Other distortions commonly encountered in photolithography (and not illustrated here) include fusion of dense features and shifting of line segment positions. Unfortunately, any distorted illumination pattern propagates to a developed resist pattern and ultimately to IC features such as polysilicon gate regions, vias in dielectrics, etc. As a result, the IC yield is degraded or the reticle design becomes unusable.
To remedy this problem, a reticle correction technique known as optical proximity correction (“OPC”) has been developed. Optical proximity correction involves adding dark regions to and/or subtracting dark regions from a reticle design at locations chosen to overcome the distorting effects of diffraction and scattering. Typically, OPC is performed on a digital representation of a desired IC pattern. First, the digital pattern is evaluated with software to identify regions where optical distortion will result. Then the optical proximity correction is applied to compensate for the distortion. The resulting pattern is ultimately transferred to the reticle glass. OPC is described generally at the end of this document.
FIG. 1C
illustrates how optical proximity correction may be employed to modify the reticle design shown in FIG.
1
A and thereby better provide the desired illumination pattern. As shown, a corrected reticle
140
includes three base rectangular features—
142
,
144
, and
146
—outlined in chromium on a glass plate
150
. Various “corrections” have been added to these base features. Some correction takes the form of “serifs”
148
a-
148
f
and
149
a-
149
f.
Serifs are small appendage-type addition or subtraction regions typically made at corner regions on reticle designs. In the example shown in
FIG. 1C
, the serifs are square chromium extensions protruding beyond the corners of base rectangles
142
,
144
, and
146
. These features have the intended effect of “sharpening” the corners of the illumination pattern on the wafer surface. In addition to serifs, the reticle
140
includes segments
151
a-
151
d
to compensate for feature thinning known to result from optical distortion.
FIG. 1D
shows a hypothetical “corrected” illumination pattern
160
produced on a wafer surface
160
by radiation passing through the reticle
140
. As shown, the illuminated region includes a light region
168
surrounding a set of dark regions
162
,
164
and
166
which rather faithfully represent the intended pattern shown in FIG.
1
A. Note that the illumination pattern shown in
FIG. 1B
of an uncorrected reticle has been greatly improved by use of an optical proximity corrected reticle.
OPC, as now practiced, involves modifying a digital representation of a reticle design such as that shown in FIG.
1
A. The modification is performed by a computer such as workstation having appropriate software for performing OPC. Points separated by less than the critical dimension on the design are evaluated in sequence and corrected as necessary. Evaluation of each point requires analysis of surrounding features in two-dimensions to determine whether problematic diffraction effects are likely. If so, an appropriate correction (serif or segment removal, for example) is performed.
A problem with using OPC when performing a full mask design correction is that a substantial commitment must be made in terms of time and computing power in order to optically correct the integrated circuit design, such as an ASIC design. For example, a moderately complex integrated circuit design may require at least a few days to correct with OPC even when the OPC algorithm runs on the fastest modern workstations. Often an ASIC will be attractive to a customer only if it can be designed in a relatively short period of time. If the time committment is too great, then other integrated circuits such as programmable logic devices may look more appealing. Further, an ASIC designer may need to perform a full-mask design OPC on tens of thousands of ASIC designs annually. Accordingly, a significant time and computing commitment must be invested in order to perform OPC on all of a designer's ASIC designs.
The computational expense of OPC can be understood by recognizing as pointed out that the correction often involves adding multiple small serifs to corners of design features and removing from, adding to, or displacing lateral sections of lines. First, these many small modifications greatly increase a p
Dou Shumay
Eib Nicholas K.
Pasch Nicholas F.
Yates Colin D.
Beyer Weaver & Thomas
LSI Logic Corporation
Siek Vuthe
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