System and method for performing on-chip self-testing

Details System and method for performing on-chip self-testing System and method for performing on-chip self-testing

2006-10-24

2006-10-24

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

C714S716000, C714S742000

Reexamination Certificate

active

07127648

ABSTRACT:
A method for determining whether a physical layer device under test is defective may include establishing a closed communication path between a verified physical layer device and the physical layer device under test via an optical interface of the verified physical layer device and an optical interface of the physical layer device under test. Alternately, the electrical interface may also be used for testing. A packet generator may transmit test packets over the established closed communication path and at least a portion of the test packets from the physical layer device under test may be received by the verified physical layer device. Subsequently, the verified physical layer device may compare at least a portion of the received test packets with at least a portion of the generated test packets in order to determine whether the physical layer device is defective or operational.

REFERENCES:
patent: 5455832 (1995-10-01), Bowmaster
patent: 6260167 (2001-07-01), Lo et al.
patent: 2002/0056060 (2002-05-01), Saruhashi et al.
patent: 2002/0059545 (2002-05-01), Nakashima et al.
patent: 2003/0035473 (2003-02-01), Takinosawa
patent: 2004/0017780 (2004-01-01), Tazebay et al.

Affiliated with

Also associated with

Rating

System and method for performing on-chip self-testing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for performing on-chip self-testing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for performing on-chip self-testing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3649946