System and method for performing floating point store folding

Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing

Reexamination Certificate

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C712S225000

Reexamination Certificate

active

11054686

ABSTRACT:
A system for performing floating point arithmetic operations including a plurality of stages making up a pipeline, the stages including a first stage and a last stage. The system also includes a register file adapted for receiving a store instruction for input to the pipeline, where the data associated with the store instruction is dependent on a previous operation still in the pipeline. The system further includes a store register adapted for outputting the data associated with the store instruction to memory and a control unit having instructions. The instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the last stage in the pipeline to the store register for use by the store instruction if the previous operation immediately precedes the store operation in the pipeline and if there is a data type match between the store instruction and the previous operation. In addition, the instructions are directed to inputting the store instruction into the pipeline and to providing a path for forwarding the data associated with the store instruction from the first stage in the pipeline to the store register for use by the store instruction if the previous operation precedes the store operation by one or more stage in the pipeline and if there is a data type match between the store instruction and the previous operation.

REFERENCES:
patent: 5615350 (1997-03-01), Hesson et al.
patent: 5878242 (1999-03-01), Olson et al.
patent: 5974538 (1999-10-01), Wilmot, II
patent: 6049860 (2000-04-01), Krygowski et al.
patent: 6289437 (2001-09-01), Eisen et al.
patent: 6408379 (2002-06-01), Juffa et al.

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