Electrical computers and digital processing systems: processing – Processing control – Branching
Patent
1998-01-16
2000-03-28
Eng, David Y.
Electrical computers and digital processing systems: processing
Processing control
Branching
G06F 940
Patent
active
060444606
ABSTRACT:
A processor is provided which performs relative addressing using the exception program counter. In one embodiment, a pipelined processor is provided with an exception program counter (EPC) register chain for tracking exception re-entry points in the instruction stream, and the instruction pipeline is provided with access to at least one of the registers in the register chain. The pipeline includes a fetch stage, a decode stage, and an execute stage. The exception PC register is identified by the decode stage as an operand in a memory access instruction for the execute stage to operate on. The execute stage then adds the contents of the exception PC register to the contents of a processor register or to a literal value to determine a target memory address.
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Eckner Hartvig
Giles Christopher M.
Eng David Y.
Kivlin B. Noel
LSI Logic Corporation
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