System and method for PC-relative address generation in a microp

Electrical computers and digital processing systems: processing – Processing control – Branching

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

G06F 940

Patent

active

060444606

ABSTRACT:
A processor is provided which performs relative addressing using the exception program counter. In one embodiment, a pipelined processor is provided with an exception program counter (EPC) register chain for tracking exception re-entry points in the instruction stream, and the instruction pipeline is provided with access to at least one of the registers in the register chain. The pipeline includes a fetch stage, a decode stage, and an execute stage. The exception PC register is identified by the decode stage as an operand in a memory access instruction for the execute stage to operate on. The execute stage then adds the contents of the exception PC register to the contents of a processor register or to a literal value to determine a target memory address.

REFERENCES:
patent: 3614741 (1971-10-01), McFarland et al.
patent: 3771138 (1973-11-01), Celtruda et al.
patent: 3787673 (1974-01-01), Watson
patent: 3875391 (1975-04-01), Shapiro et al.
patent: 4075704 (1978-02-01), O'Leary
patent: 4112489 (1978-09-01), Wood
patent: 4240139 (1980-12-01), Fukuda
patent: 4366536 (1982-12-01), Kohn
patent: 4399507 (1983-08-01), Cosgrove et al.
patent: 4819165 (1989-04-01), Lenoski
patent: 4829424 (1989-05-01), Lee
patent: 4990910 (1991-02-01), Takashima et al.
patent: 5081574 (1992-01-01), Larsen et al.
patent: 5184229 (1993-02-01), Saito et al.
patent: 5226129 (1993-07-01), Ooi et al.
patent: 5280593 (1994-01-01), Bullions et al.
patent: 5371711 (1994-12-01), Nakayama
patent: 5400075 (1995-03-01), Savatier
patent: 5408622 (1995-04-01), Fitch
patent: 5438668 (1995-08-01), Coon et al.
patent: 5440404 (1995-08-01), Okamoto
patent: 5463699 (1995-10-01), Wilkinson
patent: 5479527 (1995-12-01), Chen
patent: 5481364 (1996-01-01), Ito
patent: 5481693 (1996-01-01), Blomgren et al.
patent: 5510785 (1996-04-01), Segawa et al.
patent: 5510788 (1996-04-01), Jeong et al.
patent: 5539401 (1996-07-01), Kumaki et al.
patent: 5550542 (1996-08-01), Inoue
patent: 5568646 (1996-10-01), Jaggar
"Power PC 601", Motorola Inc., 1993, pp. 3.1-3.2, 3.42-3.43.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

System and method for PC-relative address generation in a microp does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for PC-relative address generation in a microp, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for PC-relative address generation in a microp will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1335600

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.