Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-11-08
2005-11-08
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06964029
ABSTRACT:
An embodiment of the invention includes a system for partitioning a control-flow graph representation into a reconfigurable portion and an instruction processor portion. Another embodiment of the invention includes a method of partitioning a control-dataflow graph representation that includes dividing the control-dataflow graph into two or more partition blocks, comparing the estimated performance of at least one of the partition blocks as reconfigurable logic versus instruction processor code; and assigning said at least one of the partition blocks to reconfigurable hardware or an instruction processor based on said comparing step.
REFERENCES:
patent: 5230057 (1993-07-01), Shido et al.
patent: 5570040 (1996-10-01), Lytle et al.
patent: 5737766 (1998-04-01), Tan
patent: 5892962 (1999-04-01), Cloutier
patent: 5903771 (1999-05-01), Sgro et al.
patent: 6023755 (2000-02-01), Casselman
patent: 6052773 (2000-04-01), DeHon et al.
patent: 6076152 (2000-06-01), Huppenthal et al.
patent: 6192439 (2001-02-01), Grunewald et al.
patent: 6226776 (2001-05-01), Panchul et al.
patent: 6546477 (2003-04-01), Russo et al.
Agarwal, A., et al., “The Raw Compiler Project”, pp. 1-12, http://caq-www.lcs.mit.edu/raw, Proceedings of the Second SUIF C mpiler W rkshop, Aug. 21-23, 1997.
Albaharna, Osama, t al., “On the viability of FPGA-based integrated coprocessors”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 206-215.
Amerson, Rick, et al., “Teramac—Configurable Custom Computing”, © 1995 IEEE, Publ. No. 0-8186-7086-X/95, pp. 32-38.
Barthel, Dominique Aug. 25-26, 1997, “PVP a Parallel Video coPr cessor”, Hot Chips IX, pp. 203-210.
Bertin, Patrice, et al., “Pr grammable activ mem ries: a perf rmance assessment”, © 1993 Massachusetts Institute f Technol gy, pp. 88-102.
Bittner, Ray, et al., “Computing kernels implemented with a w rmhole RTR CCM”, © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 98-105.
Buell, D., et al. “Splash 2: FPGAs in a Custom Computing Machine—Chapter 1—Custom Computing Machines: An Introduction”, pp. 1-1, http://www.computer.org/espress/catalog/bp07413/spls-ch1.html (originally believed published in J. of Supercomputing, vol. IX, 1995, pp. 219-230.
Casselman, Steven, “Virtual Computing and The Virtual Computer”, © 1993 IEEE, Publ. No. 0-8186-3890-T/93, pp. 43-48.
Chan, Pak, et al., “Architectural tradeoffs in field-programmable-device-based computing systems,”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 152-161.
Clark, David, et al., “Supporting FPGA microprocessors through retargetable software tools”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 195-103.
Cuccaro, Steven, et al., “The CM-2X: a hybrid CM-2/Xilink prototype”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 121-130.
Culbertson, W. Bruce, et al., “Exploring architectures for volume visulatization on the Teramac custom computer”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 80-88.
Culbertson, W. Bruce, et al. “Defect tolerance on the Teramac custom computer”, © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 116-123.
Dehon, Andre, “DPGA-Coupled microprocessors: commodity IC for the early 21stcentury”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 31-39.
Dehon, A., et al., “Matrix A Reconfigurable Computing Device with Confugurable Instruction Distribution”, Hot Chips IX, Aug. 25-26, 1997, Stanford, California, MIT Artificial Intelligence Laboratory.
Dhaussy, Philippe, et al., “Global control synthesis for an MIMD/FPGA machine”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 72-81.
Elliott, Duncan, et al., “Computational Ram: a memory-SID hybrid and its application to DSP”, © 1992 IEEE, Publ. No. 0-7803-0246-X/92, pp. 30.6.1-30.6.4.
Fortes, Jose, et al., “Systolic arrays, a survey of seven projects”, © 1987 IEEE, Publ. No. 0018-9162/87/0700-0091, pp. 91-103.
Gokhale, M., et al., “Processing in Memory: The Terasys Massively Parallel PIM Array” © Apr. 1995, IEEE, pp. 23-31.
Gunther, Bernard, et al., “Assessing Document Relevance with Run-Time Reconfigurable Machines”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 10-17.
Hagiwara, Hiroshi, et al., “A dynamically microprogrammable computer with low-level parallelism”, © 1980 IEEE, Publ. No. 0018-9340/80/07000-0577, pp. 577-594.
Hartenstein, R. W., et al., “A General Approach in System Design Integrating Reconfigurable Accelerators,” http://xputers.informatik.uni-ki.de/papers/paper026-1.html, IEEE 1996 Conference, Austin, TX, Oct. 9-11, 1996.
Hartenstein, Reiner, et al., “A reconfigurable data-driven ALU for Xputers”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 139-146.
Hauser, John et al.: “GARP: a MIPS processor with a reconfigurable co-processor”, © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 12-21.
Hayes, John, et al., “A microprocessor-based hypercube, supercomputer”, © 1986 IEEE, Publ. No. 0272-1732/86/1000-0006, pp. 6-17.
Herpel, H.-J., et al., “A Reconfigurable Computer for Embedded Control Applications”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 111-120.
Hogl, H., et al., “Enable++: A s cond generati n FPGA processor”, © 1995 IEEE, Publ. No. 0-8186-7086-X/95, pp. 45-53.
King, William, et al., “Using MORRPH in an industrial machine vision system”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 18-26.
Manohar, Swaminathan, et al., “A pragmatic approact t syst lic design”, © 1988 IEEE, Publ. No. CH2603-9/88/0000/0463, pp. 463-472.
Mauduit, Nicolas, et al., “Lneuro 1.0: a piece of hardware LEGO for building neural network systems,”, © 1992 IEEE, Publ. N . 1045-9227/92, pp. 414-422.
Mirsky, Ethan, A., “Coarse-Grain Reconfigurable Computing”, Massachusetts Institute of Technology, Jun. 1996.
Mirsky, Ethan, et al., “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 157-166.
Morley, Robert E., Jr., et al., “A Massively Parallel Systolic Array Processor System”, © 1988 IEEE, Publ. N . CH2603-9/88/0000/0217, pp. 217-225.
Patterson, David, et al., “A case for intelligent DRAM: IRAM”, Hot Chips VIII, Aug. 19-20, 1996, pp. 75-94.
Peterson, Janes, et al., “Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 178-187.
Schmit, Herman, “Incremental reconfiguration for pipelined applications,” © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 47-55.
Sitkoff, Nathan, et al., “Implementing a Genetic Algorithm on a Parallel Custom Computing Machine”, Publ. No. 0-8186-7086-X/95, pp. 180-187.
Stone, Harold, “A logic-in-memory computer”, © 1970 IEEE, IEEE Transactions on Computers, pp. 73-78, Jan. 1990.
Tangen, Uwe, et al., “A parallel hardware evolvable computer POLYP extended abstract”, © 1997 IEEE, Publ. No. 0-8186-8159/4/97, pp. 238-239.
Thornburg, Mike, et al., “Transformable Computer”, © 1994 IEEE, Publ. No. 0-8186-5602-6/94, pp. 674-679.
Tomita, Shinji, et al., “A computer low-level parallelism QA-2”, © 1986 IEEE, Publ. No. 0-0384-7495/86/0000/0280, pp. 280-289.
Trimberger, Steve, et al., “A time-multiplexed FPGA”, © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 22-28.
Ueda, Hirotada, et al., “A multiprocessor system utilizing enhanced DSP's for image procesing”, © 1998 IEEE, Publ. No. CH2603-9/88/0000/0611, pp. 611-620.
Villasenor, John, et al., “Configurable computing”, © 1997 Scientific American, Jun. 1997.
Wang, Qui
Hammes Jeffrey
Krause Lisa
Poznanovic Daniel
Steidel Jon
Hogan & Hartson LLP
Kubida William J.
Lembke Kent A.
SRC Computers, Inc.
Whitmore Stacy A.
LandOfFree
System and method for partitioning control-dataflow graph... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for partitioning control-dataflow graph..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for partitioning control-dataflow graph... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3494024