Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-09
2005-08-09
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C714S025000
Reexamination Certificate
active
06928629
ABSTRACT:
In one embodiment, the invention is directed to a method of processing a database comprising information regarding hardware design language (“HDL”) events occurring during a simulation of a hardware design. The method comprises identifying in the database all HDL events comprising observability events; obtaining from each of the identified observability HDL events information pertaining to a signal driving the identified observability HDL event observed on an observability bus; and creating a data structure comprising a plurality of entries, wherein each of the entries corresponds to one of the signals observed on the observability bus and contains signal information pertaining to the one of the observed signals.
REFERENCES:
patent: 5437037 (1995-07-01), Furuichi
patent: 6466898 (2002-10-01), Chan
patent: 6742166 (2004-05-01), Foster et al.
patent: 2003/0023941 (2003-01-01), Wang et al.
patent: 2003/0182642 (2003-09-01), Schubert et al.
patent: 2004/0006751 (2004-01-01), Kawabe et al.
Vo et al., “Scan parallel loading in VHDL”, Mar. 16-19, 1998, Verilog HDL conference and VHDL International Users Forum, IVC/VIUF, pp.: 178-187.
Alves da Silva et al., “A pattern analysis approach for topology determination, bad data correction and missing measurement estimation in power systems”, Oct. 15-16, 1990, Power Symposium, Proceedings of the 22 Annual North American, pp.:363 372.
Levitt et al., “Testability, debuggability, and manufacturability features of the UltraSPARC-I microprocessor”, Oct. 21-25, 1995, Test Conference, 1995. Proceedings., International, pp.: 157-166.
Bart Vermeulen and Sandeep Kumar Goel; “Design for Debug: Catching Design Errors in Digital Chips”; IEEE Design & Test of Computers; May-Jun. 2002; pp. 37-45.
Hewlett--Packard Development Company, L.P.
Rossoshek Helen
Thompson A. M.
LandOfFree
System and method for parsing HDL events for observability does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for parsing HDL events for observability, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for parsing HDL events for observability will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3458699