Computer graphics processing and selective visual display system – Computer graphics display memory system – For storing compressed data
Reexamination Certificate
2000-08-04
2004-06-22
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
For storing compressed data
C345S547000, C345S559000
Reexamination Certificate
active
06753874
ABSTRACT:
FIELD OF THE INVENTION
The invention generally relates to a video graphics workstation and, more particularly, the invention relates to the packing and unpacking of video data.
BACKGROUND OF THE INVENTION
In general, a video graphics workstation is a system of hardware and software that allows a user to process a video signal for use in a number of different applications. For example, the user may process a video signal for display on a computer monitor, for storage on a computer-readable storage medium, for display on a television, or for storage on a video tape.
Typically, however, video graphics workstations are designed to process particular video signals. Thus, most video graphics workstations are not scalable. In other words, most video graphics workstations are not designed to adapt to the changing needs of the workstation's user.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, a method and apparatus for unpacking pixels from one or more contiguous memory devices comprises loading a shift-down register with the pixel data contained in a first memory device, the first memory device having a first bit storage capacity, the shift-down register having a second bit storage capacity, the second bit storage capacity being greater than the first bit storage capacity. The method and apparatus then shifts one complete pixel of pixel data down the shift-down register, continuing to shift complete pixels of pixel data down the shift-down register until the shift-down register contains a number of bits of pixel data less than a complete pixel of pixel data. Next, the method and apparatus loads a shift-up register with the pixel data contained in a second memory device, the second memory device having the first bit storage capacity, the shift-up register having the second bit storage capacity, and shifts the pixel data in the shift-up register up the number of bits of pixel data remaining in the shift-down register. Last, the method and apparatus moves the shifted-up pixel data from the bit locations in the shift-up register to the same bit locations in the shift-down register.
In an alternate embodiment of the invention, the number of bits of pixel data remaining in the shift-down register may be zero.
In accordance with another aspect of the invention, a method and apparatus for packing pixels into contiguous memory devices, the pixels represented with pixel data, comprises providing a first memory device and a shift-up register, the first memory device having a first bit storage capacity and the shift-up register having a second bit storage capacity, the second bit storage capacity being greater than the first bit storage capacity. The method and apparatus then shifts one complete pixel of pixel data up the shift-up register, continuing to shift complete pixels of pixel data up the shift-up register until the shift-up register contains a number of bits of pixel data greater than the first bit storage capacity. Next, the method and apparatus moves the pixel data located in the uppermost bit locations of the shift-up register to the same bit locations in a shift-down register, the number of pixel data moved equal to the first bit storage capacity, the shift-down register having the second first bit storage capacity, and shifts the moved pixel data in the shift-down register down the number of bits of pixel data remaining in the shift-up register. Last, the method and apparatus outputs the pixel data in the shift-down register to the first memory device.
In an alternate embodiment of the invention, the number of bits of pixel data remaining in the shift-up register may be zero.
In further alternate embodiments of both aspects of the invention, the first bit storage capacity may be 64-bits in length and the second bit storage capacity may be 80-bits in length. In addition, one complete pixel of pixel data may be between 1-bit in length and 32-bits in length. Further, one complete pixel of pixel data may include a bit stream of color data, a bit stream of alpha data, or a bit stream of color data and alpha data. The bit stream of color data may be RGB color data or YUV-Type color data. The bit stream of color data and alpha data may be RGBA color data and alpha data or YUVA color data and alpha data.
REFERENCES:
patent: 5859790 (1999-01-01), Sidwell
Ford Jeff S.
Jordan Craig
McKinney Arthur
Bella Matthew C.
Lee & Hayes PLLC
Quillen Allen E
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