Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-12-27
2004-08-03
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
06772293
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to instruction and data requests sent from a microprocessor to system memory, and in particular relates to mechanisms to improve the scheduling of requests onto a system bus.
BACKGROUND OF THE INVENTION
Microprocessors send read and write requests to load data from or store data in various memory locations. Such memory locations include local sources within the microprocessor unit, known as local caches, and also include external system memory. To communicate requests with the system memory, requests are first placed on a system bus that operates at a bus clock rate that is often lower than the microprocessor clock rate. Due in part to the lower system clock rate, it is generally more efficient to execute requests via the local caches than the system memory. However, use of the local caches is limited by their relatively finite memory resources.
To take advantage of the limited, but more efficient resources of the local caches, requests may first be sent to the local caches for execution, whereupon if the local caches do not contain the relevant data the request is rejected and then scheduled to be placed onto the system bus. Such requests are called “pending” requests, waiting to be placed on the system bus having exhausted local resources.
But before requests are sent to either local or system memory, they are generally temporarily stored in a request queue in a buffer. In one type of buffer, known as a circular buffer, a pointer steps consecutively through accumulated request entries, automatically starting at the beginning again after the end of the buffer has been reached. When the pointer reaches a pending request, that entry is placed onto the system bus for communication to system memory.
The general bus-request scheduling system described often operates sub-optimally because there is no mechanism to distinguish between read and write requests. Each time a read request and a write request are executed in succession, or vice versa, a turnaround time penalty is paid in switching from one request type to the other.
Another problem associated with the circular buffer scheduling system is that requests issued from the microprocessor that are designed to be executed in a particular order may be placed onto the system bus out of order. The reordering occurs because of the rotation of the buffer pointer and also because of differences in processing latency between the local caches and system memory.
Furthermore, the circular buffer system has no means to distinguish low priority cache eviction requests from regular read and writes. Cache eviction requests arise when a local cache is filled to capacity. When read requests are executed and data is retrieved from system memory, an entry is allocated within a local cache to store the retrieved data. In the process of allocating a new entry, other entries may need to be evicted from the cache. However, the data that the local cache eliminates may contain updated information that is not reflected in system memory. To ensure that the data is not lost completely, the evicted data needs to be loaded into system memory as a precaution. This necessary measure, however, should not necessarily be attributed with the same priority as a regular read or write request because the data may not be required for some time.
REFERENCES:
patent: 4959771 (1990-09-01), Ardini et al.
patent: 5584038 (1996-12-01), Papworth et al.
patent: 6134634 (2000-10-01), Marshall et al.
patent: 6460114 (2002-10-01), Jeddeloh
patent: 6473832 (2002-10-01), Ramagopal et al.
Carlson Ryan L.
Espinosa Gustavo P.
Kim JunSeong
Sundararaman Ramacharan
Ellis Kevin L.
Intel Corporation
LandOfFree
System and method for optimizing memory bus bandwidth... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for optimizing memory bus bandwidth..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for optimizing memory bus bandwidth... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3274738