System and method for optimizing exceptions

Details System and method for optimizing exceptions System and method for optimizing exceptions

2005-11-08

2005-11-08

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06964027

ABSTRACT:
A method and system of optimizing exceptions to default timing constraints for use in integrated circuit design tools is described. A list of exceptions is accessed and optimized to generate a new list of exceptions. Optimizations may include: elimination of redundant information, resolution of conflicting information, and other transformations. The new list allows more efficient timing analysis, synthesis, placement, routing, noise analysis, power analysis, reliability analysis, and other operations to be performed by EDA tools.

REFERENCES:
patent: 6496972 (2002-12-01), Segal
patent: 6678644 (2004-01-01), Segal

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