System and method for optimizing clock speed generation in a...

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reissue Patent

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C713S322000, C713S323000, C713S600000, C711S154000, C327S044000

Reissue Patent

active

RE042293

ABSTRACT:
The present invention relates to a method of reducing a clock speed of a host bus to extend battery life and its operating time when a battery is supplying electric energy for a portable computer. A bus clock controlling apparatus according to the present invention includes power mode detecting means detecting a current power mode, the power mode indicative of which power source supplies the portable computer with electric energy; and clock adjusting means adjusting frequency of an applied clock from a clock generator based on the detected power mode by said power mode detecting means, and applying the frequency-adjusted clock to one or more controlling devices. Due to this invention, an electric energy stored in a battery equipped in a portable computer is saved, as a result, the battery life is extended.

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