Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2007-06-07
2010-10-05
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Branching
Reexamination Certificate
active
07809933
ABSTRACT:
A system and method for optimizing the branch logic of a processor to improve handling of hard to predict indirect branches are provided. The system and method leverage the observation that there will generally be only one move to the count register (mtctr) instruction that will be executed while a branch on count register (bcctr) instruction has been fetched and not executed. With the mechanisms of the illustrative embodiments, fetch logic detects that it has encountered a bcctr instruction that is hard to predict and, in response to this detection, blocks the target fetch from entering the instruction buffer of the processor. At this point, the fetch logic has fetched all the instructions up to and including the bcctr instruction but no target instructions. When the next mtctr instruction is executed, the branch logic of the processor grabs the data and starts fetching using that target address. Since there are no other target instructions that were fetched, no flush is needed if that target address is the correct address, i.e. the branch prediction is correct.
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patent: 6823447 (2004-11-01), Hay et al.
Aragon et al.; Power-Aware Control Speculation through Selective Throttling; 2003; ISHPCA '03.
Black et al.; Perceptron-based Confidence Estimation for Value Prediction; 2004; IEEE.
Tendler et al., “POWER4 System Microarchitecture”, IBM Corporation, Technical White Paper, Oct. 2001, pp. 1-33.
Levitan David S.
Sauer Wolfram
Chan Eddie P
Faherty Corey
Gerhardt Diana R.
International Business Machines - Corporation
Walder, Jr. Stephen J.
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