Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2005-05-10
2005-05-10
Chace, Christian P. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S118000, C710S039000, C710S054000, C370S392000, C370S412000, C370S419000
Reexamination Certificate
active
06892285
ABSTRACT:
A technique for implementing a novel high-speed high-density packet buffer utilizing a combination of high-speed and low-speed memory devices. The novel packet buffer is organized as a plurality of first-in-first-out (FIFO) queues where each FIFO queue is associated with a particular input or output line. Each queue comprises a high-speed cache portion that resides in high-speed memory and a low-speed high-density portion that resides in low-speed high-density memory. Each high-speed cache portion contains FIFO data that contains head and/or tail information associated with a corresponding FIFO queue. The low-speed high-density portion contains FIFO data that is not contained in the high-speed cache portion. A queue identifier (QID) directory refills the high-speed portion of one or more queues with data from a corresponding low-speed portion. Queue head start and end offsets are used to determine whether a corresponding queue is empty.
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Key Kenneth M.
Mak Kwok Ken
Sun Xiaoming
Cesari and McKenna LLP
Chace Christian P.
Cisco Technology Inc.
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