Electronic digital logic circuitry – Tri-state
Reexamination Certificate
2011-05-24
2011-05-24
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Tri-state
C326S086000
Reexamination Certificate
active
07948269
ABSTRACT:
In one embodiment, an output driver is disclosed. The output driver has a first driving device (Q1) that has a first terminal coupled to a bus line terminal, and a second driving device (Q2) that has a first terminal coupled to the bus line terminal. The first driving device (Q1) is configured to couple the bus line terminal to a reference voltage when activated by a first control signal, and the second driving device (Q2) is configured to couple the bus line terminal to a first supply voltage (Vcc) when the second driving device (Q2) is activated by a second control signal. The output driver also has a controller configured to activate the second control signal after the first control signal is deactivated. The second control signal remains active for a first fixed period of time.
REFERENCES:
patent: 5023488 (1991-06-01), Gunning
patent: 5210449 (1993-05-01), Nishino et al.
patent: 5210499 (1993-05-01), Walsh
patent: 5436577 (1995-07-01), Lee
patent: 5729152 (1998-03-01), Leung et al.
patent: 5914616 (1999-06-01), Young et al.
patent: 6201743 (2001-03-01), Kuroki
patent: 6218858 (2001-04-01), Menon et al.
patent: 7714618 (2010-05-01), Chen
patent: 2002/0145445 (2002-10-01), Iizuka
patent: 2005/0275425 (2005-12-01), Lee
JEDEC Standard “Gunning Transceiver Logic (GTL) Low-Level, High Speed Interface Standard for Digital Integrated Circuits”, JESD8-3A (Revision of JESD8-3, Nov. 1993, JEDEC Solid State Technology Association, May 2007, 10 pages.
Texas Instruments, “GTL/BTL: A Low Swing Solution for High-Speed Digital Logic”, Application Report, Advanced System Logic Products, SCEA003A, Mar. 1997, 25 pages.
Intel, “Intel Xeon Processor with 533 MHz Front Side Bus at 2 GHz to 3.20 GHz”, Document No. 252135-006, Feb. 2004, 94 pages.
Fairchild Semiconductor, Application Note, “GTLP vs. GTL: A Performance Comparison from a System Perspective”, AN-1070, Feb. 1997 revised Dec. 2000, 8 pages, www.fairchildsemi.com.
Ballantyne Richard S.
Paluszkiewicz Mark
Styles Henry E.
Wittig Ralph D.
Cuenot Kevin T.
Nise Benjamin E.
Tan Vibol
White Dylan
Xilinx , Inc.
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