System and method for multi processor memory testing

Details System and method for multi processor memory testing System and method for multi processor memory testing

2006-11-28

2006-11-28

Lamarre, Guy J. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S723000, C714S042000, C714S036000

Reexamination Certificate

active

07143321

ABSTRACT:
A method for testing the memory in a system with two or more processing units is provided that generally involves the following acts. The memory is divided into two or more sections—one for each of the two or more processing units. Thus, each processing unit has an associated memory section. The memory is then checked with each memory section being checked with its associated processing unit. The act of checking the memory includes causing the address of a first encountered faulty location to be stored and causing a flag to be set in response to encountering a second faulty location. Finally, it is determined whether the flag has been set after the memory is checked. If so, a walk-through routine is then performed.

REFERENCES:
patent: 4972416 (1990-11-01), Nagai et al.
patent: 5233614 (1993-08-01), Singh
patent: 5673388 (1997-09-01), Murthi et al.
patent: 6480982 (2002-11-01), Chan et al.

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