Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-10
2003-06-17
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C430S030000
Reexamination Certificate
active
06581202
ABSTRACT:
FIELD OF THE INVENTION
This present invention relates generally to the manufacture of printed circuit boards. More particularly this system relates to the measurement and analysis of printed circuit board distortions encountered during production and compensating for such distortions.
BACKGROUND TO THE INVENTION
The manufacture of printed circuit boards (PCBs) involves a succession of processing steps, some of which convert a circuit design of multiple layers to images, patterns, or circuits that will be transposed to a base material for subsequent processing into electrical interconnections. The design may be directly imposed on a production medium or on a drawing or graphical representation medium. Most usually the design is converted to a digital data representation. Conversion to a digital data representation may be accomplished with commercially available Computer Aided Design (CAD) software. The CAD program, in concert with a computer aided manufacture (CAM) program, translates the design data to a “layout” of a series of items such as circuits, interconnection holes and solder masks to be placed on the base material panel. The layout is usually transposed to a medium called artwork although the layout may also be directly transposed via a laser. The items are referred to as features. Ultimately, sections of the panel will be combined to make a PCB which in many cases are multi-layered.
Features can be applied via a photographic process onto the base material panel using an artwork or directly imaged e.g. laser imaging. During manufacture, dimensional changes of the base material will cause a difference between the anticipated location of a feature and the actual location of that feature. Spacing of a feature is particularly important so as to not short out or interfere with adjacent circuits. Further when the feature is an interconnection hole on a multi-layered circuit board, it is particularly important that these holes be aligned correctly with features in layers above or below. The location of the feature or hole relative to others is known as its “registration”. If there are misregistrations on the circuit board then subsequent processes such as drilling and further imaging operations may potentially result in misalignments with those further features. In instances of gross misregistration, the resulting product will be out of tolerance and scrapped. Often elements are placed on the panel with special marker information or easily recognizable design so as to easily measure movement that occur in the manufacturing process. These elements will be referred to as “targets”.
Correction of errors in manufacture has been the subject of much development. For example, U.S. Pat. No. 4,890,239 to Ausschnitt, et al. was issued for a “Lithographic Process Analysis and Control System.” This system is a system and method for modelling the necessary focus and exposure required when one is imaging features of particular dimensions. The system has ramifications for PCB manufacture, however it does not deal with how to measure the distortion of PCB material and how to correct that distortion.
U.S. Pat. No. 4,799,175 to Sano, et al. was issued for a “System for Inspecting Pattern Defects of Printed Wiring Boards.” The invention comprises very specific equipment for measuring PCB defects for characterizing the quality of resultant PCBs using targets on the PCB. There is no mention of how to correct for the errors that are present.
U.S. Pat. No. 4,967,381 was issued to Lane, et al. for a “Process Control Interface System for Managing Measurement Data.” This invention is a system for obtaining measurement data for process control and trend analysis purposes. While data can be taken using this invention, the corrective action required is not disclosed.
U.S. Pat. No. 5,206,820 to Ammann, et al. was issued for a “Metrology System for Analyzing Panel Misregistration in a Panel Manufacturing Process and Providing Appropriate Information for Adjusting Panel Manufacturing Processes.” This patent describes the process of creating targets known as “fiducials” on a glass master. The targets are placed in the corner of the master and are subsequently measured. Errors are characterized for any particular phase of the manufacturing process and monitored so that the contribution of the various errors can be reduced as much as possible. Targets are not placed throughout the PCB panel and thus might miss certain types of distortion. Further, corrective action is not discussed.
U.S. Pat. No. 5,495,535 to Smilansky, et al. was issued for a “Method of Inspecting Articles.” This system has the goal of inspecting articles and detecting errors for subsequent monitoring of a process which might also include PCB manufacture. The system stores points and compares the stored points to the actual points. Corrective action is not described however.
U.S. Pat. No. 5,519,633 was issued to Chang, et al. for a “Method and Apparatus for the Cross-Sectional Design of Multi-Layer Printed Circuit Boards.” This invention relates to the design and manufacture of circuit boards and does attempt to minimize errors associated with the manufacturing. The tracking of such errors via targets of different types is not discussed.
U.S. Pat. No. 5,497,331 was issued to Iriki, et al. for a “Semiconductor Integrated Circuit Device Fabrication Method and Its Fabrication Apparatus.” This invention is designed to enhance the yield of integrated circuit devices. No targets are used during the course of this particular invention or the equipment associated therewith.
U.S. Pat. No. 6,070,004 to Prein was issued for a “Method of Maximizing Chip Yield for Semiconductor Wafers.” Again, this is an invention that relates to integrated circuit design. It is designed to maximize chip yield over an entire wafer. However, there are no targets involved in the process nor is there an attempt to model any systematic errors introduced during the manufacturing process.
U.S. Pat. No. 5,960,185 was issued to Nguyen for a “Method and Apparatus for Wafer Disposition Based On Systematic Error Modelling.” This system relates to integrated circuits and for modelling the errors that are systematic and might be introduced during the course of integrated circuit manufacture. However, this system models various error sources that relate to the positioning of a mask and not to the migration of the material itself. Thus, this patent relates principally to mask alignment and errors based on a known library of errors that can occur with mask alignment. There are no targets involved in the process, nor is material migration dealt with in any fashion.
U.S. Pat. No. 6,030,154 was issued to Whitcomb, et al. for a “Minimum Error Algorithm/Program.” This patent relates to multi-layer printed circuit boards and for minimizing the error associated with drilling holes to connect the circuits of one layer with another. The system involves taking x-rays of the various layers and determining the optimum location for drilling between layers. While this process does involve trying to compensate for errors in material movement, there is no attempt to measure the material movement in any systematic way for the purpose of minimizing the errors during subsequent manufacture.
In the manufacture of PCBs, in order to reduce build up of positional errors during manufacture, each process requiring registration of an image to the product must apply compensations to the image positioning of the features to allow for the material movement. Compensations are determined by historical data of compensations required for similar product or by producing a small run of boards to determine the compensations required. To monitor and control the manufacturing processes, measurements are taken of feature and target positions during production. These measurements are compared with the specifications.
As noted above current methods of measurement use targets located in the corners of the panel or artwork and base compensation calculations on the difference in pitch between the measured targets and the require
Jones Steve
Kelley Andrew
Tourné Joseph A. A. M.
Dunlap Codding & Rogers P.C.
Siek Vuthe
Viasystems Group, Inc.
LandOfFree
System and method for monitoring and improving dimensional... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for monitoring and improving dimensional..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for monitoring and improving dimensional... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3160861