Computer-aided design and analysis of circuits and semiconductor – Design of semiconductor mask or reticle – Layout generation
Reexamination Certificate
2008-08-11
2011-11-29
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Design of semiconductor mask or reticle
Layout generation
Reexamination Certificate
active
08069423
ABSTRACT:
Some embodiments provide a method for optimally decomposing patterns within particular spatial regions of interest on a particular layer of a design layout for a multi-exposure photolithographic process. Specifically, some embodiments model the spatial region using a mathematical equation in terms of two or more intensities. Some embodiments then optimize the model across a set of feasible intensities. The optimization yields a set of intensities such that the union of the patterns created/printed from each exposure intensity most closely approximates the patterns within the particular regions. Based on the set of intensities, some embodiments then determine a decomposition solution for the patterns that satisfies design constraints of a multi-exposure photolithographic printing process. In this manner, some embodiments achieve an optimal photolithographic printing of the particular regions of interest without performing geometric rule based decomposition.
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Ghan Justin
Sezginer Abdurrahman
Adeli & Tollen LLP
Bowers Brandon
Cadence Design Systems Inc.
Chiang Jack
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