System and method for minimizing page tables in virtual memory s

Details System and method for minimizing page tables in virtual memory s System and method for minimizing page tables in virtual memory s

1997-03-19

2000-06-06

Cabeca, John W.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711202, 711206, 711221, G06F 926

Patent

active

060732261

ABSTRACT:
The invention described herein works in conjunction with a processor having an address translation cache that is updated by referencing a page table directory and a plurality of associated page tables referenced by the page table directory. The page table directory and a single page table are configured to generate a memory fault whenever the processor attempts to update its address translation cache. In response to such a memory fault, a memory fault handler temporarily loads a single page table entry with the needed address translation. In addition, the memory fault handler initializes the page table directory so that it references the single page table entry that has been loaded. Control is then returned from the memory fault handler, and the processor obtains the address translation. In response to a subsequent memory fault, the memory fault handler invalidates the previously loaded entry, and loads whatever address translation is currently needed by the processor. The address translations are cached in the processor's translation lookaside buffer.

REFERENCES:
patent: 5630087 (1997-05-01), Talluri et al.
patent: 5668968 (1997-09-01), Wu
patent: 5696927 (1997-12-01), MacDonald et al.
patent: 5724538 (1998-03-01), Morris et al.
patent: 5752275 (1998-05-01), Hammond

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