Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
1999-09-30
2002-11-26
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C365S185030
Reexamination Certificate
active
06487685
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of data error detection and correction and more particularly to an improved system and method for minimizing error correction code bits in variable sized data formats.
BACKGROUND OF THE INVENTION
In digital electronic systems, information is represented in binary format (1's and 0's). One type of digital electronic system is a computer system. When binary information is passed from one point to another in a computer system, errors may occur. For example, a 1 bit may be interpreted as a 0 bit or a 0 bit may be interpreted as a 1 bit. These errors may be caused by media defects, electronic noise, component failures, poor connections, deterioration due to age, and other factors. When a bit is mistakenly interpreted from a bit source such as internal memory or a storage device, a bit error has occurred. Error detection and correction is the process of detecting bit errors and correcting them. Error detection and correction may be done in software or hardware. One type of error detection and correction system uses error correcting codes (ECC) stored with data to verify the integrity of that data as it is transferred within a computer system. An example of an ECC system is a standard single error correcting, double error detecting (SEC-DED) system. The number of ECC bits stored with the data depends upon the number of bits of data. For example, using SEC-DED, twenty-six bits of data requires six ECC bits and fifty-seven bits of data requires seven ECC bits.
Multiprocessor computers include several processors with each processor having an associated memory. In certain multiprocessor architectures, such as cache-coherent non-uniform memory access (ccNUMA) architectures, processors may access and use any memory within the multiprocessor computer. In directory based multiprocessor computers, a memory directory entry shows the state of every cache line in memory. Multiprocessor computers include several processors capable of operating in parallel. Scalable multiprocessor computers may be sized with a variable number of processors to meet a particular need. In order to minimize the amount of storage required to store directory entries in scalable multiprocessor computers, variable sized memory directory formats may be used where the memory directory size depends upon the number of processors in the multiprocessor computer. Since multiple memory directory formats and sizes may be used, a different number of ECC bits may be needed by each memory directory format. Since it is inefficient and wasteful to implement separate ECC logic for each memory directory format, it is desirable to implement an ECC logic scheme where each memory directory format uses the minimum number of bits for ECC error detection and correction while at the same time using the same ECC logic.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated that a need has arisen for a system and method for minimizing error correction code bits in variable sized data formats that minimizes the number of ECC bits and uses the same ECC logic for multiple data formats. In accordance with the present invention, a system and method for minimizing error correction code bits in variable sized data formats are provided that substantially eliminate and reduce disadvantages and problems associated with providing error correction code logic for variable sized data formats.
According to an embodiment of the present invention, a method for minimizing ECC bits in variable sized data formats is provided that comprises determining the number of ECC bits needed for each of a plurality of data formats. The method then creates a common data representation for using a single implementation of error detection and correction logic for all of the plurality of data formats. The common data representation is equal in size to the largest data format in the plurality of data formats and, thus, requires the same number of ECC bits as the largest data format. The method then chooses an ECC matrix and default values for unused data bits in the common data representation such that for smaller data formats, any ECC bits beyond the minimum required for that sized data format will have known values thereby allowing smaller data formats to go through the error detection and correction logic using the common data representation. The method then retrieves a data entry from memory where the data entry has one of the plurality of data formats. The method then formats the data entry into the common data representation. The method then populates unused bits in the common data representation with chosen default values. The chosen default values are chosen to provide known values for any ECC bits that are only needed for larger data formats thereby minimizing the number of ECC bits stored in each of the plurality of data formats. The method then generates a syndrome for the common data representation using the ECC matrix. The method then detects errors in the common data representation in response to the syndrome including any number of “1” bits. The method then corrects errors in the common data representation using the syndrome and the ECC matrix. The method then reformats the common data representation into a format of the retrieved data entry.
The present invention provides various technical advantages over conventional systems and methods for minimizing ECC bits in variable sized data formats. For example, one technical advantage is minimizing the number of ECC bits for each of multiple data formats. Another technical advantage is reusing error detection and correction logic as well as ECC bit generation logic for the multiple data formats. Other technical advantages may be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 5418796 (1995-05-01), Price
patent: 5754566 (1998-05-01), Christopherson et al.
patent: 6209113 (2001-03-01), Roohparvar
McCracken David E.
Stuart Fiske James A.
Baker & Botts L.L.P.
Moise Emmanuel L.
Silicon Graphics Inc.
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