Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-02-26
2002-01-01
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S146000, C711S140000, C711S122000, C711S217000, C712S217000, C712S219000, C710S039000
Reexamination Certificate
active
06336168
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to the execution of load instructions in a processor.
BACKGROUND INFORMATION
In order to increase the operating speed of microprocessors, architectures have been designed and implemented that allow for the execution of multiple parallel load instructions within the microprocessor. Pipelining of instructions permits more than one instruction to be issued for execution substantially in parallel. A problem with such a process occurs when a first load instruction is sent for execution but incurs a cache miss, and then a second load instruction is sent for execution for loading the same cache line as the first load instruction. Typically, in such a situation, the second load instruction would have to be re-executed, or at least wait for the load data from the first load instruction to be retrieved into the primary data cache and validated before the second load instruction could be completed.
As a result, there is a need in the art for an improved process for executing pipelined load instructions within a processor.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing need by merging pairs of load instructions that address the same cache line in certain situations. The present invention provides a load store unit reference that accepts a load instruction to a cache line that is previously missed in the cache. A load miss queue holds the information needed to handle the cache miss of a previous load instruction. When a subsequent load instruction attempts a load from the same cache line that previously missed in the cache, the load miss queue accepts responsibility for the second load instruction. When the cache line is returned to the data cache, the requested data is passed to the register of the first load instruction over a first bus, and the requested data of the second load instruction is passed over a second bus to the register of the second load instruction. Thus, the operands for each of the two load instructions that access the same cache line are both serviced by the same miss operation.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 5826109 (1998-10-01), Abramson et al.
Frederick, Jr. Marlin Wayne
Ronchetti Bruce Joseph
Shippy David James
Thatcher Larry Edward
England Anthony V. S.
Kordzik Kelly K.
Song Jasmine
Winstead Sechrest & Minick P.C.
Yoo Do Hyun
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