Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-08-31
2001-09-18
Thai, Tuan V. (Department: 2752)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S222000, C714S746000, C714S754000
Reexamination Certificate
active
06292869
ABSTRACT:
CROSS REFERENCES TO RELATED APPLICATIONS
U.S. patent application Ser. No. 09/144,593 entitled “SYSTEM AND METHOD FOR MEMORY SELF-TIMED REFRESH FOR REDUCED POWER CONSUMPTION”, filed concurrently herewith is assigned to the same assignee hereof and contains subject matter related, in certain respect, to the subject matter of the present application. The above-identified patent application is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This invention relates to correction of soft errors in computer memory by scrubbing. More particularly, it relates to scrub operations which interrupt SDRAM memory STR mode.
2. Background Art
Dynamic Random Access Memory (DRAM) chips need to have the charge in their array cells periodically refreshed to retain the data contents. This refresh is normally initiated by commands issued by a memory controller external to the DRAMs. Synchronous DRAMs (SDRAMs) provide a mode, Self-Timed Refresh (STR) mode, during which the SDRAM initiates refresh internally provided no read or write accesses to memory occur. Computer SDRAM memory subsystems utilize less power for STR mode verses externally initiated refresh.
Further to reduce power consumption, SDRAM memory can be put in a self-timed refresh mode during which read or write requests are not allowed. A memory controller would typically wait for an interval of no memory activity (such as, reads or writes) before causing SDRAMs to enter STR mode.
Soft errors in computer memory are often corrected by scrubbing. Scrubbing refers to periodically or otherwise reading data, correcting any correctable errors, and writing the corrected data back to memory.
If scrubbing is suspended when the memory is in self-timed refresh mode, soft errors can accumulate in the memory. If scrubbing is not suspended during self-time refresh (STR) mode, the memory must exit self-timed refresh to execute the scrubbing operation. After the scrubbing operation, if another interval of time is waited and there are no system or I/O read or write requests to memory, unnecessary power is consumed.
It is an object of the invention to provide an improved memory controller.
It is a further object of the invention to provide an improved controller system and method for memory refresh and scrub operations.
It is a further object of the invention to provide for reduced power memory refresh and scrub operations.
SUMMARY OF THE INVENTION
In accordance with the invention, a system and method is provided for scrubbing computer storage. Upon detecting an interval of storage inactivity, external storage refresh commands are inhibited and the storage is placed in self timed refresh (STR) mode. Upon detecting storage activity while storage is in STR mode, STR mode is terminated. Upon detecting a scrub request while storage is in STR mode, STR mode is terminated and thereafter the scrub request is executed. Upon completing execution of the scrub request, storage is returned to STR mode.
Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.
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Gerchman Edward T.
Gildea Mark C.
Jensen Randall S.
Anderson Matthew D.
Beckstrand Shelley M
International Business Machines - Corporation
Thai Tuan V.
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