Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-05
2004-05-18
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06738953
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to a system and method for efficiently characterizing a memory instance.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that various types of circuitry such as analog blocks, non-volatile memory (e.g., read-only memory or ROM), random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take several staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design reuse is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well known that memory is a key technology driver for SOC design. It is also well known that speed and power consumption are two of the more significant factors in designing a high performance memory instance, whether provided as a stand-alone device or in an embedded application. In order to ensure that a memory circuit operates in an optimal manner as per design, the device is rigorously characterized during its design phase with respect to several key performance criteria. Typically, timing parameters such as cycle time (t
cc
), clock-to-Q delay (t
cq
), et cetera, are estimated by running simulations on a suitable parametric netlist (e.g., an RC netlist) extracted from the memory circuit's layout. Whereas extracting parametric netlists for memory instances is a relatively straightforward process, it becomes highly cumbersome when high density memory is involved because of the large amounts of data generated thereby. Not only do the storage requirements for such data quickly reach unmanageable levels, but the engineering time necessary to perform full-scale characterization of a memory device becomes prohibitive as well.
State-of-the-art solutions to address these concerns generally involve the use of what are known as PI-models for estimating the various resistive and capacitive loadings that give rise to the delay in a memory circuit. Although these solutions are fairly effective with respect to reducing engineering time and database storage requirements, they are nevertheless beset with several deficiencies and shortcomings. For example, it is commonly known that the use of PI-models, which are based on transmission line techniques, for estimating memory loadings gives rise to inaccurate results, thereby throwing off the timing estimates by a significant percentage. In general, such inaccuracies are due to inadequate representation of the secondary and higher-order electrical effects (e.g., capacitive coupling) inherent in memory circuits. Also, where an end user of memory (e.g., a value-added system integrator) is desirous of fine-tuning a memory circuit to suit its specific applications, there exists a critical lack of appropriate knowledge such that building necessary PI-models is out of the question. Furthermore, the current solutions are also unsatisfactory with respect to memory circuit power estimations.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an efficient memory characterization system and method using a hierarchically-stitched netlist generation technique that advantageously overcomes these and other aforementioned deficiencies of the state-of-the-art solutions. Based on the physical architecture (i.e., floor plan) of a memory instance, which may be an embedded memory circuit or a stand-alone device, a plurality of repeatable blocks or tiles are generated with respect to each distinct section of the floor plan. The array portion of the memory instance is thus segmented into a number of bitcell array tiles arranged as rows and columns spanning the array, wherein each bitcell array tile comprises a select number of cells in rows and columns. An individual bitcell array tile is accordingly associated with a predetermined number of wordlines (WLs) and bitlines (BLs). Similarly, the row decoder (X-DEC) section of the memory instance is also correspondingly segmented into a column of vertically-stacked row decoder tiles, wherein each row decoder tile is operable to be coupled to a select row of bitcell array tiles via a select number of WLs. The input/output (I/O) block of the memory instance is analogously segmented into a row of horizontally-stacked I/O tiles as well, each I/O tile corresponding to a specified number of BLs. The control block of the memory instance is preferably provided as a single tile having connections to the vertically-stacked row decoder tiles as well as the horizontally-stacked I/O tiles.
The repeatable tiles, also referred to as leaf cells, thus comprise the entire memory instance and are preferably created depending on a minimum area required to encompass an optimal number of memory strap points relating to the global signals that span the memory instance. I/O pins (or, nodes) are defined for each tile with respect to the global signals in horizontal and vertical directions as the case may be. A parametric dataset is obtained for each tile using an extractor (where the memory instance is in post-layout condition) or a pre-layout wire-delay estimator. The parametric netlist for the entire memory instance is assembled thereafter by appropriately coupling the individual parametric datasets using the I/O pins of the tiles with respect to the global signals.
In a further aspect, the present invention is directed to a computer-accessible medium operable in connection with a processor environment, wherein the computer-accessible medium carries a sequence of instructions which, when executed in the processor environment, cause the various steps involved in the memory characterization scheme of the present invention as summarized hereinabove.
REFERENCES:
patent: 5548524 (1996-08-01), Hernandez et al.
patent: 5822218 (1998-10-01), Moosa et al.
patent: 6212668 (2001-04-01), Tse et al.
patent: 6408422 (2002-06-01), Hwang et al.
patent: 6470489 (2002-10-01), Chang et al.
patent: 2001/0052062 (2001-12-01), Lipovski
Sabharwal Deepak
Shubat Alex
Danamraj & Youst P.C.
Smith Matthew
Tat Binh C.
Virage Logic Corp.
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