Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Reexamination Certificate
2005-10-25
2010-02-23
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
Reexamination Certificate
active
07669034
ABSTRACT:
A method and data processing system for accessing an entry in a memory array is provided using base and offset addresses without adding the base and offset addresses. PGZO encoding is performed on the address bits of the operands. The PGZO values are evaluated using wordline generators resulting in a plurality of possible memory array entry addresses. In parallel with the PGZO operations, a carry value is generated using other bits in the operands. The result of the carry operation determines which of the possible memory array entries is selected from the memory array.
REFERENCES:
patent: 3265876 (1966-08-01), Lethin
patent: 5754819 (1998-05-01), Lynch et al.
patent: 6813628 (2004-11-01), Bhushan et al.
patent: 2003/0110198 (2003-06-01), Park
patent: 2004/0064674 (2004-04-01), Asano et al.
J. Cortadella et al., “Evaluation of A+B=K Conditions Without Carry Propagation,” IEEETrans. on Computers, vol. 41, No. 11, Nov. 1992.
J. Cortadella et al., “Evaluation of A+B=K Conditions in Constant Time,”IEEE ISCAS, 1988.
Y. Lee et al., “Address Addition and Decoding without Carry Propagation,” IEICE Trans. Inf. & Syst., vol. E80-D, No. 1, Jan. 1997.
R. Heald et al., “64-kbyte Sum-Addressed-Memory Cache with 1.6ns Cycle and 2.6ns Latency,” IEEE JSSC, vol. 33, No. 11, Nov. 1998.
W. Lynch et al., “Low Load Latency through Sum-Addressed Memory (SAM)”.
International Search Report and Written Opinion for correlating PCT Patent Application No. PCT/US06/40017, Applicant's file reference SC13805TC, dated May 19, 2008.
U.S. Appl. No. 11/552,817; Non-final Office Action dated Aug. 20, 2009.
Bearden David R.
Hockstra George P.
Ramaraju Ravindraraj
Dare Ryan
Dolezal David G.
Freescale Semiconductor Inc.
Kim Matt
VanLeeuwen & VanLeeuwen
LandOfFree
System and method for memory array access with fast address... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for memory array access with fast address..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for memory array access with fast address... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4207535