Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
1999-06-08
2004-01-06
Broda, Samuel (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S014000, C703S016000, C714S038110, C714S039000, C714S741000
Reexamination Certificate
active
06675138
ABSTRACT:
FIELD AND BACKGROUND OF THE INVENTION
The present invention relates to a system and method for detecting and measuring coverage of a functional verification programming environment during test generation, and in particular, to a system and method for detecting and measuring such coverage over time as the simulation is performed.
Design verification is the process of determining whether an integrated circuit, board, or system-level architecture, exactly implements the requirements defined by the specification of the architecture for that device. Design verification for a device under testing (DUT) may be performed on the actual device, or on a simulation model of the device. For the purposes of explanation only and without intending to be limiting in any way, the following discussion centers upon testing which is performed on simulation models of the device.
As designs for different types of devices and device architectures become more complex, the likelihood of design errors increases. However, design verification also becomes more difficult and time consuming, as the simulation models of the design of the device also become more complex to prepare and to test.
The problem of design verification is compounded by the lack of widely generalizable tools which are useful for the verification and testing of a wide variety of devices and device architectures. Typical background art verification methods have often been restricted to a particular device having a specific design, such that the steps of preparing and implementing such verification methods for the simulation model must be performed for each new device.
The process of verifying a design through a simulation model of the device is aided by the availability of hardware description languages such as Verilog and VHDL. These languages are designed to describe hardware at higher levels of abstraction than gates or transistors. The resultant simulated model of the device can receive input stimuli in the form of test vectors, which are a string of binary digits applied to the input of a circuit. The simulated model then produces results, which are checked against the expected results for the particular design of the device. However, these languages are typically not designed for actual verification. Therefore, the verification engineer must write additional programming code in order to interface with the models described by these hardware description languages in order to perform design verification of the device.
Examples of testing environments include static and dynamic testing environments. A static testing environment drives pre-computed test vectors into the simulation model of the DUT and/or examines the results after operation of the simulation model. In addition, if the static testing environment is used to examine the results which are output from the simulation model, then errors in the test are not detected until after the test is finished. As a result, the internal state of the device at the point of error may not be determinable, requiring the simulation to be operated again in order to determine such internal states. This procedure consumes simulation cycles, and can require the expenditure of considerable time, especially during long tests.
A more useful and efficient type of testing is a dynamic testing environment. For this type of environment, a set of programming instructions is written to generate the test vectors in concurrence with the simulation of the model of the DUT and while potentially being controlled by the state feedback of the simulated device. This procedure enables directed random generation to be performed and to be sensitive to effects uncovered during the test itself on the state of the simulation model of the device. Thus, dynamic test generation clearly has many advantages for design verification.
Within the area of testing environments, both static and dynamic testing environments can be implemented only with fixed-vector or pre-generation input. However, a more powerful and more sophisticated implementation uses test generation to produce the environment.
One example of such a test generator is disclosed in U.S. patent application Ser. No. 09/020,792, filed on Feb. 6, 1998, incorporated by reference as if fully set forth herein. This test generation procedure interacts with, and sits as a higher level over, such hardware description languages as Verilog and VHDL. The test generation procedure is written in a hardware-oriented verification specific object-oriented programming language. This language is used to write various tests, which are then used to automatically create a device verification test by a test generator module. A wide variety of design environments can be tested and verified with this language. Thus, the disclosed procedure is generalizable, yet is also simple to program and to debug by the engineer.
The disclosed language features a number of elements such as structs for more richly and efficiently describing the design of the device to be simulated by the model. Unfortunately, the disclosed language and resultant test generation environment does not include features for testing the state of the device over time. Such testing is performed by sampling the values for various variables at different times, either according to some triggering event or at predetermined times, and is termed “temporal coverage”. Temporal coverage is a collection of coverage information based on the occurrence of some pattern in time, with the pattern itself being defined according to a temporal language. Temporal coverage differs from automatic coverage, which is triggered by the appearance of a line of code or other static event, in that temporal coverage is driven by the occurrence of events in time. Temporal coverage enables the behavior of the device to be monitored over time during the testing period, particularly since a circuit or other DUT cannot be exhaustively simulated, such that all possible states are tested. Analysis of the coverage enables the designer to determine which states of the device require further testing.
Although such a testing capability would therefore be very useful to have, temporal coverage of the testing environment is not currently available, although temporal languages are known in the background art. For example, the Lustre language, which is designed for programming real-time systems, has an associated temporal logic (Halbwachs N., et al., Sixth International Symposium on Lucid and Intensional Programming, ISLIP '93, Quebec, April 1993). However, the Lustre language, like other currently available temporal languages, does not provide a mechanism for determining exact points when data is to be sampled in order to provide temporal coverage. Thus, there is no currently available combination of temporal coverage provided through a user-defined temporal language for determining coverage of the simulation of the DUT.
Therefore, there is an unmet need for, and it would be highly useful to have, a system and method for testing the behavior of the device over time through temporal coverage, which would enable more thorough and realistic testing of the device to be performed.
SUMMARY OF THE INVENTION
The system and method of the present invention tests the quality of a simulation model for the DUT (device under test) through temporal coverage of the testing and verification process. Temporal coverage examines the behavior of selected variables over time, according to a triggering event. Such a triggering event could be determined according to fixed, predefined sampling times and/or according to the occurrence of a temporal pattern of state transitions as defined by a temporal expression given in a temporal language, for example. This information is collected during the testing/verification process, and is then analyzed in order to determine the behavior of these variables, as well as the quality of the simulation model for the DUT. For example, the temporal coverage information can be analyzed to search for a coverage hole, indicated by the absence of a particular
Hollander Yoav
Kashai Yaron
Plotnikov Lev
Broda Samuel
G. E. Ehrlich (1995) Ltd.
Phan Thai
Verisity Ltd.
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