Oscillators – Ring oscillators
Reexamination Certificate
2002-04-09
2004-05-04
Shingleton, Michael B. (Department: 2817)
Oscillators
Ring oscillators
C331S10800D, C331S17700V, C327S158000, C324S762010
Reexamination Certificate
active
06731179
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a test device and method for measuring the true effects of negative bias temperature instability (NBTI) of PFETs (p-channel field effect transistors).
2. Description of the Related Art
High performance PFETs (p-channel field effect transistors) with p+ polysilicon doped gates have been found to exhibit an instability after voltage/temperature aging. This phenomenon is known as “negative bias temperature instability” (NBTI). The instability occurs under negative gate voltage and is measured as an increase in the magnitude of threshold voltage of the device. Higher stress temperatures produce more degradation. The mechanism is known to cause reliability performance degradation for the PFET because of this change in threshold voltage.
Several physical models have been proposed in the literature. Basically, an electro-chemical reaction presumably occurs in the gate oxide, due to sensitivity of p+ gates to moisture trapping. The result is a net positive charge in the gate oxide, causing a bias effect that affects threshold voltage.
The degradation caused is exponential with oxide electric field. This problem is getting much worse with each generation of CMOS scaling in which oxide thickness is aggressively scaled down but voltage scaling does not keep pace with the oxide thickness scaling. The mechanism, therefore, becomes a major technology reliability scaling problem.
A relaxation of the degradation has been observed when the DC stress is turned “OFF” following an “ON” stress. Relaxation is a phenomenon known to occur in charge trapping mechanisms.
A stress bias configuration of the PFET
10
is shown in
FIG. 1
, where a positive voltage
16
is applied to the diffusions
13
,
14
and the N-well
12
while the gate
15
of the PFET is at ground potential. This stress bias configuration can alternatively be replaced by the configuration shown in
FIG. 2
where a negative voltage
21
is applied to the gate while all other terminals of the FET are at ground.
FIG. 3
shows the effect of stress on the drain-to-source current versus gate voltage characteristic
30
of the FET
10
. The bias temperature aging under the configuration of
FIG. 1
produces an increase
31
in the absolute value of the threshold voltage (Î″V
th
), which in turn causes a decrease in the drain-to-source current (I
d
) for a given gate-to-source voltage (V
g
). Again, this PFET device instability is usually referred to as a negative bias temperature instability (NBTI) since it requires the applications of a negative gate voltage for the mechanism to be active. The change in threshold voltage and the corresponding decrease in device current could cause signal delay or performance degradation in operating circuits utilizing such devices.
There are numerous publications dealing with the characteristics, behavior and physics of the NBTI mechanism. From this literature, it is found that the magnitude of change in threshold voltage after stress for a time duration t under gate voltage of V and temperature T is given by:
|&Dgr;
V
th
|=A e
(−&Dgr;H/KT)
e
(−&ggr;Tox/V)
t
n
(Equation 1),
where |Î″V
th
| is the magnitude of final threshold voltage value after stress minus its initial value before stress; A, Î
3
, and n are constants (positive values) that are dependent upon the particular technology in question; Î″H is referred to as the activation energy; Tox is the oxide thickness, and K is Boltzmann's constant.
FIG. 4
shows a typical behavior of |Î″V
th
| with a straight line relationship (slope=n) versus time on a log—log scale, as predicted by equation (1). The behavior of the NBTI mechanism described in the literature is the DC stress mode where the stress conditions of
FIG. 1
are applied. This DC stress mode of
FIG. 1
will be referred to as the “ON” stress condition, and the behavior of |Î″V
th
| in this case is given by equation (1).
The increase in the absolute value of the threshold voltage due to the NBTI mechanism is a serious technology reliability problem because it leads to performance degradation and subsequent failure of semiconductor integrated chips. Because this mechanism depends on oxide thickness, as shown in the above equation 1, the degradation caused by the NBTI becomes worse as the oxide thickness is reduced (i.e., as CMOS technology scaling continues and as the drive for better performance intensifies). An important aspect of dealing with this problem is the ability to determine the actual impact of this mechanism on the reliable performance of integrated chips where devices are mostly subjected to pulsed voltage conditions rather than DC conditions.
This is illustrated in
FIG. 5
, which shows a simple CMOS inverter
50
where the input voltage changes from ground potential to a value of V with a period of Ï
″
, and the output voltage is the complement of the input. Excluding transient conditions, the PFET of this CMOS inverter is subjected to two stress configurations. The first configuration is when the output voltage is equal to V, i.e., the gate of the PFET is at ground, and this condition is what has been referred to as the “ON” stress condition.
The second configuration, as shown in
FIG. 6
, is referred to as the “OFF” stress condition, i.e., when the gate
15
of the PFET
10
is at voltage V, one diffusion is also at voltage V while the other diffusion is at ground. But, as mentioned above, the behavior of the NBTI mechanism is represented by equation (1) as a DC “ON” stress.
More realistic to the actual operation of the CMOS inverter, the more realistic question is that of asking what happens to the device under conditions of an “ON” stress, followed by an “OFF” stress.
FIG. 7A
(Case
1
) shows the behavior of |Î″V
th
| versus time when the PFET is subjected to an “ON” stress (A) for a duration of 20 seconds, followed by an “OFF” stress (B) for a duration of 1200 seconds with measurements of |Î″V
th
| (readouts) at 10 sec, 20 sec, 60 sec., 180 sec., and 1200 sec. (all measured from the start of the “OFF” stress), and then followed by another “ON” stress (A′) for a duration of 20 seconds. The magnitude of the stress voltage was 4.2 V, and the stress temperature was 140° C.
Even though the magnitude of the threshold voltage shift (C) was small under these conditions, it is noticeable that the “OFF” stress following the “ON” stress caused |Î″V
th
| to decrease measurably. Thus, there is some relaxation effect due to the “OFF” stress following the “ON” stress.
In
FIG. 7B
, the behavior of Case
1
shown in
FIG. 7A
was replotted. This time the effective time (A, A′) under “ON” stress condition is indicated on the X-axis of the plot (meaning that all time intervals for “OFF” stress were not included on the X-axis). The Y-axis for |Î″V
th
| of
FIG. 7B
includes the relaxation effect of the “OFF” stress. It is clear that the behavior of the PFET under pulsed voltage conditions, i.e., repeated combinations of “OFF” and “ON” stressing, would be more complicated than the DC model under “ON” stress, and thus it would be extremely difficult to theoretically predict the actual effect of the NBTI mechanism on the performance of CMOS integrated circuits, and to determine the effect of technology scaling and the effect of different processing conditions.
Thus, a system needs to be developed to determine the impact of the NBTI reliability mechanism on the performance of CMOS integrated circuits, under any conditions of cycle time (Ï
″
), which is the sum of the intervals for the “ON” plus “OFF” stresses (Ï
″
=1/f, where f is the frequency or performance), duty factor (DF), which is “ON” time relative to cycle time, and technology processing. Prior to the present invention, no such system has been known.
FIG. 8
illustrates the use of appliqués
Abadeer Wagdi William
Ellis Wayne Frederick
Hansen Patrick R.
McKenna Jonathan M.
Henkler, Esq. Richard A.
International Business Machines - Corporation
McGinn & Gibb PLLC
Shingleton Michael B.
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