Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2000-10-30
2004-10-19
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S164000
Reexamination Certificate
active
06807602
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to data processing techniques and, in particular, to a system and method for efficiently storing data produced by one or more processing units.
2. Related Art
Large computer systems (or servers) often employ a plurality of memory units to provide enough instruction and data memory for various applications. Each memory unit has a large number of memory locations of one or more bits where data can be stored, and each memory location is associated with and identified by a particular memory address, referred to hereafter as “memory unit address.” When an instruction that stores data is executed, a bus address defined by the instruction is used to obtain a memory unit address, which identifies the memory location where the data is actually to be stored. In this regard, a mapper is often employed that maps or translates the bus address into a memory unit address having a different value than the bus address. There are various advantages associated with utilizing bus addresses that are mapped into different memory unit addresses.
For example, many computer applications are programmed such that the bus addresses are used consecutively. In other words, one of the bus addresses is selected as the bus address to be first used to store data. When a new bus address is to be utilized for the storage of data, the new bus address is obtained by incrementing the previously used bus address.
If consecutive bus addresses are mapped to memory unit addresses in the same memory unit, then inefficiencies may occur. In this regard, a finite amount of time is required to store and retrieve data from a memory unit. If two consecutive data stores occur to the same memory unit, then the second data store may have to wait until the first data store is complete before the second data store may occur. However, if the two consecutive data stores occur in different memory units, then the second data store may commence before the first data store is complete. To minimize memory latency and maximize memory bandwidth, consecutive bus addresses should access as many memory units as possible. This can also be described as maximizing the memory interleave.
As a result, the aforementioned mapper is often designed to map the bus addresses to the memory unit addresses such that each consecutive bus address is translated into a memory unit address in a different memory unit. For example, a bus address having a first value is mapped to a memory unit address identifying a location in a first memory unit, and the bus address having the next highest value is mapped to a memory unit address identifying a location in a second memory unit. Therefore, it is likely that two consecutive data stores from a single computer application do not occur in the same memory unit. In other words, it is likely that consecutive data stores from a computer application are interleaved across the memory units.
Backup systems are often employed to enable the recovery of data in the event of a failure of one of the memory units. For example, U.S. Pat. No. 4,849,978, which is incorporated herein by reference, describes a checksum backup system that may be used to recover the data of a failed memory unit. In this regard, one of the memory units is designated a checksum memory unit. Each address in the checksum memory unit is initialized to zero and is correlated with an address in each of the other non-checksum memory units. Each data value being stored in an address of one of the non-checksum memory units is exclusively ored with the data value previously stored in the foregoing address. The result of this exclusive or operation is then exclusively ored with the value, referred to as a “checksum value,” in the correlated address of the checksum memory unit. The result of this exclusive or operation is then stored in the foregoing correlated address of the checksum memory unit as a new checksumn value.
When a memory unit fails, the value of an address in the failed memory unit can be recovered by exclusively oring the checksum value in the correlated address of the checksum memory unit with each of the values in the other memory units that are correlated with the foregoing checksum value. Although checksum backup systems enable the recovery of data from a failed memory unit, the process of maintaining the checksum values can cause some inefficiencies, since the checksum memory unit should be updated for each data store that occurs in a non-checksum memory unit.
Thus, a heretofore unaddressed need exists in the industry for providing a more efficient data storage system and method. It is desirable for the data storage system and method to include a backup system with minimal adverse impact to the overall performance of the data storage system and method.
SUMMARY OF THE INVENTION
The present invention overcomes the inadequacies and deficiencies of the prior art as discussed hereinbefore. Generally, the present invention provides a data storage system and method for mapping bus addresses to memory unit addresses such that data value and checksum value stores associated with consecutive bus addresses occur in an interleaved fashion.
In architecture, the data storage system of the present invention utilizes a plurality of memory systems, at least one processor, and a mapping system. Each of the memory systems has memory and a memory controller for storing and retrieving data. The processor transmits requests for writing data values. These requests include bus addresses. The mapping system maps the bus addresses into memory addresses, such as the memory unit addresses previously described. The mapping system maps consecutive bus addresses such that the memory addresses mapped from the consecutive bus addresses are interleaved across a plurality of the memory systems. In response to the foregoing requests from the processor, the mapping system identifies checksum system identifiers that identify locations where checksum values to be updated based on the aforementioned data values are stored. The checksum system identifiers preferably identify each of the plurality of mapping systems so that the checksum identifiers and, therefore, the checksum updates that occur based on these checksum system identifiers are interleaved across these memory systems.
In accordance with another feature of the present invention, the mapping system optionally, but preferably, includes two mappers. One mapper maps the bus addresses to memory addresses, as described above. The other mapper maps the bus addresses to access keys that may be used to prevent unauthorized data accesses. This optional feature enables the memory of the memory systems to be allocated more efficiently.
The present invention can also be viewed as providing a method for interleaving data values and checksums across memory systems. The method can be broadly conceptualized by the following steps: providing memory systems, each of the memory systems having memory and a memory controller for storing and retrieving data; receiving requests to write data values, the requests including consecutive bus addresses; mapping the consecutive bus addresses into memory addresses; identifying each of a plurality of the memory systems based on the memory addresses; selecting checksum system identifiers in response to the requests to write data values; identifying each of the plurality of the memory systems based on the checksum system identifiers; and updating checksum values stored in each of the plurality of said memory systems based on the checksum identifiers.
Other features and advantages of the present invention will become apparent to one skilled in the art upon examination of the following detailed description, when read in conjunction with the accompanying drawings. It is intended that all such features and advantages be included herein within the scope of the present invention and protected by the claims.
REFERENCES:
patent: 3825903 (1974-07-01), Brown
patent: 4695947 (1987-09-01), Ikeda et al.
patent: 4849978 (1989-0
Hornung Bryan
Shaw Keith W.
Vogel Paul F.
Hewlett--Packard Development Company, L.P.
Kim Matthew
Thomas Shane
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