Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-05-22
2007-05-22
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
11125168
ABSTRACT:
A system and method for manipulating an integrated circuit layout allowing for reuse and migration. The method comprises steps of identifying objects in a geometric layout to generate a first symbolic layout, nesting a plurality of objects in the first symbolic layout to generate a first virtual device, and associating the first virtual device to generate a second symbolic layout. The method further comprises a step of modifying parameters and constraints of the first virtual device to generate a third virtual device, and a step of optimizing a second symbolic layout including the first virtual devices to generate a third symbolic layout based on the third virtual device. Consequently, the second symbolic layout can be reused. Further, the method comprises a step of updating parameters and constraints of the first virtual device based on new process rules to generate a fourth virtual device so that the second symbolic layout can be used to generate a third symbolic layout for migration.
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Lin Po Huang
Shih Miin Chih
Su Yi Jen
Anaglobe Technology, Inc.
Dinh Paul
Parihar Suchin
Volentine & Whitt PLLC
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