Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-01-15
2002-09-24
Kim, Matthew (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S160000
Reexamination Certificate
active
06457105
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to memory management systems, and more particularly to a system for managing data in an asynchronous input/output (I/O) cache memory.
2. Discussion of the Related Art
In computer system design, a principal objective is to continually design faster and more efficient computer systems. In this regard, most conventional high-performance computer systems include cache memories. As is known, a cache memory is a high-speed memory that is positioned between a microprocessor and main memory in a computer system in order to improve system performance. Typically, cache memories (or caches) store copies of portions of main memory data that are actively being used by the central processing unit (CPU) while a program is running. Since the access time of a cache can be faster than that of main memory, the overall access time can be reduced.
Cache memory is used in data storage systems so that under typical conditions, a relatively large and slow main memory can be accessed at a relatively high rate. The cache memory is a relatively small high-speed memory that can store, at any given time, a portion of the data stored in the main memory. The cache memory also includes a cache directory or index of the data elements stored therein. The cache directory is referenced to provide an indication of whether or not each data element is located in the cache memory at any given time, and if so, the present location of the data element in the cache memory.
A data storage system is typically responsive to data access requests from a host computer. The data access requests, for example, include read and write requests. When a data storage system having a cache memory receives a request for access to data, the cache directory is inspected to determine whether the data element to be accessed resides in the cache memory. If so, the data storage system accesses the data in the cache memory. If not, the data storage system accesses the data in the main memory, and if the accessed data is likely to be accessed again in the near future, the accessed data is copied into the cache memory.
In some data storage systems, data elements to be accessed are always copied into the cache memory if they are absent from the cache memory. Some data storage systems are also responsive to explicit “prefetch” commands from the host computer to cause specified data to be copied into the cache, even though the specified data is not immediately accessed by the host computer.
Because the cache memory has a capacity that is usually much smaller than the main memory, it is often necessary for data elements in the cache memory to be replaced or removed from the cache memory in order to provide space in the cache memory for new receiving data elements to be copied into the cache memory. In general, for the cache memory to be useful, the data elements replaced or removed from the cache memory must be less likely to be accessed in the near future than the data elements that are staged into the cache memory. This process is conventionally known as cache management.
A wide variety of methods and strategies are known for managing data within a cache memory to achieve optimum system performance. These methods often vary from system to system, and from application to application. Management methods may vary depending upon whether the cache memory is an electronic (e.g., integrated circuit) memory that is caching data on a disc drive (main memory), or whether the cache memory is a high speed electronic memory that is caching data for a slower speed electronic memory (main memory). Management methods may further vary depending upon the size of the cache memory.
Notwithstanding the various cache memory management methods, generally, when space is available within the cache memory for new data, the new data is simply copied into the available space, and logged in the directory/index of the cache. When, however, no additional space is available for new data then existing data must be discarded to make room for the new data. Also, the directory/index must be updated accordingly. As previously mentioned, there are a variety of methods that are known and implemented for determining which data within the cache to discard, each of which seeks to discard data that will not likely be used again (at least in the near term).
Notwithstanding the various known methods for cache memory management, further improvements are desired.
SUMMARY OF THE INVENTION
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the advantages and novel features, the present invention is generally directed to a system and method for providing improved memory management in an asynchronous I/O cache memory. In accordance with one aspect of the invention, a method is provided and includes the steps of identifying a request for data from the system memory by a requesting device that is in communication with the system memory via an I/O bus. Then the method controls the communication of data from the system memory into the cache memory. The method further includes the step of communicating the data from the cache memory to the requesting device, and immediately after communicating the data to the requesting device, the method discards the data from the cache memory.
In accordance with the preferred embodiment, the method flushes data from the I/O cache, one line at a time. In one implementation, a given cache line of data is flushed from the cache after the last data byte of the cache line is communicated out to the requesting device. It will be appreciated, however, that more sophisticated implementations may be employed. For example, it may be determined by a cache memory controller that the requesting device has requested a block of contiguous data, which block ends at some intermediate position within the cache line. However, consistent with the inventive concepts, upon determination that the last data byte from the block has been communicated, then the invention may immediately flush the cache line containing that last data byte. If the data block spanned more than one cache line, previous cache lines would be flushed upon communication of the last data byte from each line to the requesting device.
As a particular example, one embodiment of the present invention may identify a request for data originating from an ATM card. Recognizing that simple ATM communications occur in precise 48 byte payloads, an embodiment of the present invention can assume that precisely 48 contiguous bytes will be communicated to the requesting device. Accordingly, upon communication of the last of the 48 data bytes, this embodiment of the invention may flush the line of cache data containing the last of the 48 data bytes. If the first byte of the 48 data bytes was located in a different cache line, then that different cache line may, as mentioned above, be flushed upon communication of the last data byte from that cache line.
It will be appreciated that the present invention realizes significant performance enhancements, by recognizing that I/O traffic is usually not recurrent within a small window of time (unlike CPU instructions and certain other types of data). More particularly, significant performance gains are obtained by the invention for relatively large, contiguous data blocks, or even small data blocks, when the precise size (or ending byte) is known. For large data blocks that may consume multiple cache lines, each cache line is flushed upon communicating the last byte of the cache line out to the requesting device. Likewise, when the last byte of the requested data is known, then the cache line containin
Horning Robert J
Spencer Thomas V
Anderson Matthew D.
Hewlett--Packard Company
Kim Matthew
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