System and method for managing a cache memory

Details System and method for managing a cache memory System and method for managing a cache memory

2006-09-05

2006-09-05

Bragdon, Reginald G. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S165000, C711S109000, C711S154000

Reexamination Certificate

active

07103719

ABSTRACT:
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached data. A barrel shifter for realignment of cached data during move operations and comparators for comparing a test data string to cached data a cache line at a time may be provided.

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TMS320C80 (MVP) Transfer Controller User's Guide, Chapters 1-4, pp. TC:1-1 through 4-54, Copyright © 1995, Texas Instruments Incorporated.

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