Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
1999-07-30
2003-03-25
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S600000, C714S055000
Reexamination Certificate
active
06539492
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to computer storage systems and, more particularly, to high performance controllers for disk array systems. The controllers incorporate a system clock configuration which provides high reliability.
BACKGROUND OF THE INVENTION
Computer storage systems for high capacity, on-line applications are well known. Such systems use arrays of disk devices to provide a large storage capacity. To alleviate the delays inherent in accessing information in the disk array, a large capacity system cache memory is typically utilized. Controllers known as back end directors or disk adaptors control transfer of data from the system cache memory to the disk array and from the disk array to the system cache memory. Each back end director may control several disk devices, each typically comprising a hard disk drive. Controllers known as front end directors or host adaptors control transfer of data from the system cache memory to a host computer and from the host computer to the system cache memory. A system may include one or more front end directors and one or more back end directors.
The front end directors and the back end directors perform all functions associated with transfer of data between the host computer and the system cache memory and between the system cache memory and the disk array. The directors control cache read operations and execute replacement algorithms for replacing cache data in the event of a cache miss. The directors control writing of data from the cache to the disk array and may execute a prefetch algorithm for transferring data from the disk devices to the system cache memory in response to sequential data access patterns. The directors also execute diagnostic and maintenance routines. In general, the directors incorporate a high degree of intelligence.
Current computer storage systems are characterized by high performance and high reliability. Nonetheless, as the performance of the host computers which operate with the computer storage systems increases, it is necessary to provide computer storage systems having enhanced performance. In particular, operating speeds must be increased as the operating speeds of host computers increase. Furthermore, as the cost of computer memory decreases and program complexity increases, the volumes of data transferred increase. Because computer storage systems are frequently used in highly critical applications, reliability is an important consideration. The storage systems must remain operational, even when certain components and subsystems fail. Accordingly, the storage systems may incorporate redundant hardware and are extensively tested. Because the performance of computer storage systems is determined to a significant degree by the performance of the controllers, there is a need for very high performance, high reliability controllers for computer storage systems.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, apparatus comprises a plurality of circuit boards, each having a clock and a clock selection circuit, a backplane for mounting and interconnecting the circuit boards, the backplane including a primary clock line connected to each of the circuit boards and a secondary clock line connected to each of the circuit boards, and means for designating a first clock on a first one of the circuit boards as a primary clock and for coupling the primary clock to the primary clock line on the backplane, and for designating a second clock on a second one of the circuit boards as a secondary clock and for coupling the secondary clock to the secondary clock line on the backplane. The clock selection circuit on each of the circuit boards includes means for selecting the primary clock as the system clock for operation when the primary clock is functional and for selecting the secondary clock as the system clock for operation when the primary clock is not functional.
The clock selection circuit on each of the circuit boards may further comprise means for selecting an internal clock when the primary clock and the secondary clock are not functional. The clock selection circuit on each of the circuit boards may include a register for storing clock selection information and means for setting the clock selection information in the register.
According to a second aspect of the invention, a computer storage system comprises an array of storage devices, a system cache memory, a plurality of controller boards for controlling data transfer to and between the array of storage devices, the system cache memory and a host computer, each of the controller boards having a clock and a clock selection circuit, and a backplane for mounting and interconnecting the controller boards. The backplane includes a primary clock line and a secondary clock line connected to each of the controller boards. The computer storage system further comprises means for designating a first clock on a first one of the controller boards as a primary clock and for coupling the primary clock to the primary clock line on the backplane and for designating a second clock on a second one of the controller boards as a secondary clock and for coupling the secondary clock to the secondary clock line on the backplane. The clock selection circuit on each of the controller boards includes means for selecting the primary clock as the system clock when the primary clock is functional and for selecting the secondary clock as the system clock when the primary clock is not functional.
The backplane may further include a clock select line connected to each of the controller boards for controlling the clock selection circuit on each of the controller boards. The clock selection circuit on each of the controller boards may further comprise a clock detection circuit for detecting whether the selected clock is functional.
According to a third aspect of the invention, a method is provided for generating a system clock in a system comprising a plurality of circuit boards and a backplane for mounting and interconnecting the circuit boards. The method comprises the steps of providing a clock and a clock selection circuit on each of the circuit boards, connecting a primary clock line and a secondary clock line to each of the circuit boards on the backplane, designating a first clock on a first one of the circuit boards as a primary clock and coupling the primary clock to the primary clock line on the backplane, designating a second clock on a second one of the circuit boards as a secondary clock and coupling the secondary clock to the secondary clock line on the backplane, and selecting the primary clock as the system clock when the primary clock is functional and selecting the secondary clock as the system clock when the primary clock is not functional. An internal clock on each of the circuit boards may be selected when the primary clock and the secondary clock are not functional.
REFERENCES:
patent: 5754730 (1998-05-01), Windrem et al.
patent: 6078595 (2000-06-01), Jones et al.
patent: 6141769 (2000-10-01), Petivan et al.
patent: 6218821 (2001-04-01), Bisbee
Arsenault Brian
Bauer Rudy M.
Tung Victor W.
EMC Corporation
Gaffin Jeffrey
Kim Harold
Wolf Greenfield & Sacks P.C.
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