Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-09-16
1999-04-27
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711149, 395308, G06F 1336
Patent
active
058976566
ABSTRACT:
A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses and an I/O bus to a shared main memory and efficiently maintains cache coherency while minimizing the impact to latency and total bandwidth within the system. The system provides coherency filters which coordinate bus-to-bus communications in such a way as to maintain cache memory coherency with a small amount of cross-bus traffic. In addition, the system provides a multiported pool of memory cells which interconnect the multiple buses.
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White George P.
Chan Eddie P.
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Portka Gary J.
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