Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-05-05
1998-07-28
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711 3, 711118, 711210, 711154, G06F 1200
Patent
active
057874760
ABSTRACT:
A multiprocessor computer system and method for maintaining coherency between virtual-to-physical memory translations of multiple requestors in the system. A poison bit is associated with a memory block in the system. The poison bit is set to indicate that a virtual-to-physical memory translation for the memory block is stale. An exception is generated in response to an access by one of the requestors to the memory block if the poison bit is set, thereby indicating to the requestor that the virtual-to-physical memory translation entry for the memory block is stale. The virtual-to-physical memory translation for the memory block is then updated with a virtual memory translation corresponding to a new physical location for the memory block. In an embodiment having a cache-based multiprocessor system, the method further comprises the step of invalidating all cached copies of the memory block. In this case, the invalidating step and the setting step must be performed as an atomic operation.
REFERENCES:
patent: 4141067 (1979-02-01), McLagan
patent: 4481573 (1984-11-01), Fukunaga et al.
patent: 4622631 (1986-11-01), Frank et al.
patent: 4825412 (1989-04-01), Sager et al.
patent: 4914577 (1990-04-01), Stewart et al.
patent: 5214770 (1993-05-01), Ramanujan et al.
patent: 5226144 (1993-07-01), Moriwaki et al.
patent: 5228136 (1993-07-01), Shimizu et al.
patent: 5282274 (1994-01-01), Liu
patent: 5297269 (1994-03-01), Donaldson et al.
patent: 5361340 (1994-11-01), Kelly et al.
patent: 5398325 (1995-03-01), Chang et al.
patent: 5406504 (1995-04-01), Denisco et al.
patent: 5412787 (1995-05-01), Forsyth et al.
patent: 5437017 (1995-07-01), Moore et al.
patent: 5455834 (1995-10-01), Chang et al.
patent: 5493660 (1996-02-01), DeLano et al.
patent: 5515522 (1996-05-01), Bridges et al.
patent: 5530933 (1996-06-01), Frink et al.
patent: 5588131 (1996-12-01), Borill
Patricia J. Teller,"Translation Lookaside Buffer Consitency," Jun. 1990, pp. 26-36.
Steven K. Reinhardt, "The Wisconsin Wind Tunnel: Virtual Prototyping of Parrallel Computers," May 1993 pp. 48-60.
Laudon James P.
Lenoski Daniel E.
Silicon Graphics Inc.
Swann Tod R.
Thai Tuan V.
LandOfFree
System and method for maintaining coherency of virtual-to-physic does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for maintaining coherency of virtual-to-physic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for maintaining coherency of virtual-to-physic will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-35267