System and method for maintaining coherency and tracking...

Details System and method for maintaining coherency and tracking... System and method for maintaining coherency and tracking...

2003-10-01

2008-09-23

Peikari, B. James (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S141000, C711S145000, C711S156000

Reexamination Certificate

active

07428615

ABSTRACT:
A data processing system according to the invention comprises a processor (P) and a memory hierarchy. The highest ranked level therein is a cache coupled to the processor. The memory hierarchy comprises a higher ranked cache (C1) having a cache controller (CC1) operating according to a write allocate scheme, and a lower ranked cache (C2) is coupled to the higher ranked cache (C1) having a cache controller (CC2). The size of the higher ranked cache is smaller than the size of the lower ranked cache. Both caches (C1,C2) administrate auxiliary information (V1,V2) indicating whether data (D1,D2) present therein is valid. The line size of the lower ranked cache (C2) is an integer multiple of the line size of the higher ranked cache (C1). The auxiliary information (V1) in the higher ranked cache (C1) concerns data elements (D1) at a finer granularity than that in the lower ranked cache (C2). The higher ranked cache (C1) is arranged for transmitting a write mask (WM) to the lower ranked cache (C2) in conjunction with a line of data (DL) for indicating which data in the lower ranked cache (C2) is to be overwritten at the finer granularity. Fetching a line from the next lower ranked level (M) is suppressed if the write mask (WM) indicates that the line (DL) provided by the higher ranked cache (C1) is entirely valid in which case, the controller (CC2) of the lower ranked cache allocates the cache line in the lower ranked cache (C2) without fetching it.

REFERENCES:
patent: 6751705 (2004-06-01), Solomon et al.
patent: 2002/0087791 (2002-07-01), Arimilli et al.

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