Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-11-14
2006-11-14
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S145000, C711S144000
Reexamination Certificate
active
07136968
ABSTRACT:
An invalidation bit pattern (IBP) for maintaining transaction cache consistency in a wireless communication system is provided. The IBP comprises at least one bit corresponding to at least one cached data stored on a cache of a mobile communication terminal, wherein the bit value represents whether the corresponding cached data was updated in a communication server during a first broadcast period, said first broadcast period associated with a first time stamp; and an IBP time stamp representing time the IBP was broadcast; wherein if the difference between the IBP time stamp and the first time stamp is larger than a threshold value, then all cached data stored on the cache is replaced with updated data from the communication server; and wherein if the difference between the IBP time stamp and the first time stamp is not larger than a threshold value, then updating the corresponding cached data with updated data from the communication server, if the bit value represents that the corresponding cached data was updated.
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Bataille Pierre-Michel
Lee Hong Degerman Kang & Schmadeka
LG Electronics Inc.
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