System and method for maintaining cache coherency using path dir

Details System and method for maintaining cache coherency using path dir System and method for maintaining cache coherency using path dir

1996-08-09

1999-05-04

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711145, G06F 1300

Patent

active

059000155

ABSTRACT:
A method of maintaining cache coherency in a computer system including two or more processors sharing information, the processors coupled by two or more interconnects to a memory such that the processors are not directly coupled to the same is disclosed interconnect is disclosed. The method of maintaining cache coherency includes the steps of: accessing and sharing, by a first processor and a second processor, information from the memory and setting path indicators in directories associated with at least two of the interconnects on a respective first and second access path to the memory, and storing the information in respective associated first and second caches; and writing a new value to the information, by a writing processor sharing the information, the writing step including the steps of: invalidating other copies of the information via the path indicators; acquiring exclusive access to the information by changing the path indicators to an exclusive state; and writing the new value to the information, in response to the acquiring step.

REFERENCES:
patent: 4755930 (1988-07-01), Wilson, Jr. et al.
patent: 5018063 (1991-05-01), Liu
patent: 5197139 (1993-03-01), Emma et al.
patent: 5297269 (1994-03-01), Donaldson et al.
patent: 5313609 (1994-05-01), Baylor et al.
R. Omran et al., "An Efficient Single Copy Cache coherence Protocol for Multiprocessors with Multistage Interconnection Networks", In Proceedings of the 1994 Conference for Scalable High Performance Computing, pp. 1-8, May 1994.
R. Omran et al., "A Multi-cache Coherence Scheme for Shuffle-Exchange Network based Multiprocessors", pp. 72-79, IEEE Computer Soc. Press, Sep. 1995.
D. Chaiken et al., "Directory-Based Cache Coherence in Large-Scale Microprocessors", Computer Magazine, Jun. 1990, pp. 49-58.
D. Lenoski et al., "DASH Prototype: Logic Overhead and Performance", IEEE Transactions on Parallel and Distributed Systems, vol. 4, No. 1, Jan. 1993, pp. 41-61.
H. Mizrahi et al., "Extending the Memory Hierarchy into Multi-Interconnection networks: A Performance Analysis", 1989 International Conference on Parallel Processing, pp. I-41 to I-50.

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