System and method for maintaining cache coherency in a...

Details System and method for maintaining cache coherency in a... System and method for maintaining cache coherency in a...

2006-02-14

2006-02-14

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S130000, C711S147000, C711S133000, C710S038000, C710S022000

Reexamination Certificate

active

07000078

ABSTRACT:
A data processing system having shared memory accessible through a transaction-based bus mechanism. A plurality of system components, including a central processor, are coupled to the bus mechanism. The bus mechanism includes a cache coherency transaction within its transaction set. The cache coherency transaction comprises a request issued by one of the system components that is recognized by a cache unit of the central processor as an explicit command to perform a cache coherency operation. The transaction further comprises a response issued by the central processor indicating status of the cache coherency operation.

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