Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-10-03
2006-10-03
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C430S005000, C378S035000, C700S097000, C700S120000, C700S121000, C250S492220
Reexamination Certificate
active
07117477
ABSTRACT:
There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks.
REFERENCES:
patent: 4926489 (1990-05-01), Danielson et al.
patent: 5182718 (1993-01-01), Harafuji et al.
patent: 5308991 (1994-05-01), Kaplan
patent: 5563702 (1996-10-01), Emery et al.
patent: 5594850 (1997-01-01), Noyama et al.
patent: 5663893 (1997-09-01), Wampler et al.
patent: 5680588 (1997-10-01), Gortych et al.
patent: 5723233 (1998-03-01), Garza et al.
patent: 5737072 (1998-04-01), Emery et al.
patent: 5774222 (1998-06-01), Maeda et al.
patent: 5888675 (1999-03-01), Moore et al.
patent: 6077310 (2000-06-01), Yamamoto et al.
patent: 6078738 (2000-06-01), Garza et al.
patent: 6081659 (2000-06-01), Garza et al.
patent: 6090555 (2000-07-01), Fiekowsky et al.
patent: 6120952 (2000-09-01), Pierrrat et al.
patent: 6223139 (2001-04-01), Wang et al.
patent: 6226781 (2001-05-01), Nistler et al.
patent: 6243855 (2001-06-01), Kobayashi et al.
patent: 6272236 (2001-08-01), Pierrrat et al.
patent: 6285488 (2001-09-01), Sandstrom
patent: 6335151 (2002-01-01), Ausschnitt et al.
patent: 6370679 (2002-04-01), Chang et al.
patent: 6372391 (2002-04-01), Wolfe et al.
patent: 6397165 (2002-05-01), Fiekowsky
patent: 6405153 (2002-06-01), Fiekowsky
patent: 6449749 (2002-09-01), Stine
patent: 6453452 (2002-09-01), Chang et al.
patent: 6453457 (2002-09-01), Pierrrat et al.
patent: 6470489 (2002-10-01), Chang et al.
patent: 6504644 (2003-01-01), Sandstrom
patent: 6519501 (2003-02-01), Pierrrat et al.
patent: 6539331 (2003-03-01), Fiekowsky
patent: 6611767 (2003-08-01), Fiekowsky et al.
patent: 6687041 (2004-02-01), Sandstrom
patent: 6757645 (2004-06-01), Chang et al.
patent: 6760473 (2004-07-01), Fiekowsky
patent: 6765651 (2004-07-01), Fiekowsky et al.
patent: 6803554 (2004-10-01), Ye et al.
patent: 6806456 (2004-10-01), Ye et al.
patent: 6816302 (2004-11-01), Sandstrom et al.
patent: 6828068 (2004-12-01), Progler et al.
patent: 6828542 (2004-12-01), Ye et al.
patent: 6884984 (2005-04-01), Ye et al.
patent: 6893800 (2005-05-01), Jessen et al.
patent: 6969837 (2005-11-01), Ye et al.
patent: 6969864 (2005-11-01), Ye et al.
patent: 7003758 (2006-02-01), Ye et al.
patent: 7053355 (2006-05-01), Ye et al.
patent: 7074530 (2006-07-01), Progler et al.
patent: 2003/0107770 (2003-06-01), Klatchko et al.
patent: 2003/0138706 (2003-07-01), Progler et al.
patent: 2003/0226951 (2003-12-01), Ye et al.
patent: 2003/0233630 (2003-12-01), Sandstrom et al.
patent: 2004/0053143 (2004-03-01), Sandstrom
patent: 2004/0058255 (2004-03-01), Jessen et al.
patent: 2004/0096883 (2004-05-01), Fiekowsky et al.
patent: 2004/0119036 (2004-06-01), Ye et al.
patent: 2004/0140418 (2004-07-01), Ye et al.
patent: 2004/0184657 (2004-09-01), Lin et al.
patent: 2004/0222354 (2004-11-01), Ye et al.
patent: 2004/0225488 (2004-11-01), Wang et al.
patent: 2004/0232313 (2004-11-01), Ye et al.
patent: 2005/0076322 (2005-04-01), Ye et al.
patent: 2005/0091633 (2005-04-01), Ye et al.
patent: 2005/0097500 (2005-05-01), Ye et al.
patent: 2005/0118515 (2005-06-01), Progler et al.
patent: 2005/0120327 (2005-06-01), Ye et al.
patent: 2005/0122500 (2005-06-01), Ye et al.
patent: 2005/0166174 (2005-07-01), Ye et al.
patent: 2005/0219502 (2005-10-01), Sandstrom et al.
patent: 2006/0000964 (2006-01-01), Ye et al.
patent: 2001084369 (2001-03-01), None
“Compact Formulation of Mask Error Factor for Critical Dimension Control in Optical Lithography”, Zhang, et al., Microlithography, SPIE 2002, 4 pages.
“A Simulation Framework for Lithography Process Monitoring and Control Using Scatterometry”, Bao et al., AEC/APC 2001, 4 pages.
“A Novel Approach for Modeling and Diagnostics of Lithography Process”, Wang et al., AEC/APC 2001, 5 pages.
“Optimum sampling for characterization of systematic variation in photolithography”, Cain et al., Microlithography, SPIE 2002, 13 pages.
“Electrical linewidth metrology for systematic CD variation characterization and causal analysis”, Cain et al., Microlithography, SPIE 2003, 12 pages.
“Improved Method for Measuring and Assessing Reticle Pinhole Defects for the 100nm Lithography Node”, Taylor et al., Photomask Japan 2002, Apr. 2002.
“Mask Defect Disposition: Flux-Area Measurement of Edge, Contact, and OPC Defects Correlates to Wafer and Enables Effective Decisions”, Fiekowsky et al., Photomask Japan 2001, Paper 4409-10, Apr. 2001.
“Contact Holes: Optical Area Measurement Predicts Printability and is Highly Repeatable”, By Glen Scheid, LSI Logic Corp.; Taylor et al., Photomask Japan 2001, Paper 4409-11, Apr. 2001.
“New Optical Metrology for Masks: Range and Accuracy Rivals SEM”, Cottle et al., Photomask Japan 2001, Poster 4409-60, Apr. 2001.
“Soft Defect Printability: Correlation to Optical Flux-Area Measurements”, Taylor et al., the SPIE 20thAnnual BACUS Symposium on Photomask Technology and Management, Conference 4186, Sep. 2000.
“The End of Thresholds: Subwavelength Optical Linewidth Measurement Using the Flux-Area Technique”, Fiekowsky, Photomask Japan 2000, Poster 4066-67, Apr. 2000.
“Defect Printability Measurement in the KLA-351: Correlation to Defect Sizing Using the AVI Metrology System”, Fiekowsky et al., the SPIE 19thAnnual BACUS Symposium on Photomask Technology and Management, Conference 3873, Sep. 1999.
“Accurate and Repeatable Mask Defect Measurements for Quarter-Micron Technology”, Fiekowsky, the SPIE 17thAnnual BACUS Symposium on Photomask Technology and Management, Sep. 1997.
“The AVI Photomask Metrology System”, Automated Visual Inspection Presentation, Feb. 2002, 25 pages.
“Photomask Production Integration of KLA STARlight™ 3000 System”, Kalk et al, Proc. Of SPIE, vol. 2621, 15thAnnual BACUS Symposium on Photomask Technology and Management, Dec. 1995, pp. 112-121.
“Defect Detection and Classification in VLSI Pattern Inspection”, Soo-Ik Chae, Sep. 1987, Ph.D. Dissertation.
Cao Yu
Chen Luoqi
Chen Xun
Lu Yen-Wen
Ye Jun
Brion Tecnologies, Inc.
Kik Phallaka
Steinberg Neil A.
LandOfFree
System and method for lithography simulation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for lithography simulation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for lithography simulation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3649913