Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-12
2004-06-15
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06751785
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor processing. More specifically, systems and methods for limiting capacitance increase due to dummy fill metals utilized to improve planar profile uniformity are disclosed.
2. Description of Related Art
Typically, an integrated circuit fabrication process involves a series of layering processes in which metallization, dielectrics, and other materials are applied to the surface of a semiconductor wafer to form a layered interconnected structure. The integrated circuits formed form the wafer generally include interlayered circuits comprising a plurality of metal lines across multiple layers that are interconnected by metal-filled vias. Thus, one of the critical steps in the fabrication process is the formation of interconnects that connect the layers of the integrated circuit device, resulting in integrated circuit devices with high complexity and circuit density.
Particularly in the fabrication of sub-0.35 &mgr;m semiconductor devices, it is important that the fabrication process produces good planarization with each layer of the integrated circuits prior to subsequent layering steps in order to reduce process yield loss from those subsequent layering steps. A planarized surface is often necessary to maintain a required level of photolithographic depth of focus for subsequent steps and to ensure that metal interconnects are not deformed over contour steps.
For example, a damascene method is often employed for metallization of the interconnects between layers. The damascene method involves etching a via or trench pattern into a planar dielectric layer dow to the active region of the device. Excess metal is typically deposited over the entire wafer surface in order to fill the vias or trenches. The excess portions of the metal layer are then polished and removed down to the patterned metal surface, leaving the thin lines of metals as interconnects. As with other steps in the fabrication process, it is important that the polished interconnect damascene layer be planar.
In order to achieve the degree of planarity required to produce ultra high density integrated circuits, chemical-mechanical polishing or planarization (CMP) process is employed to planarize the topography of films or layers on the substrate. In general, the CMP process is an abrasive process that involves selective removal of material from the semiconductor wafer by rotating a polishing pad and the wafer relative to each other while applying a controlled amount of pressure in the presence of a chemical slurry. CMP can be performed on both oxides and metals and can produce good local planarization. After the CMP process, the smoothed surface is ready for subsequent process steps, such as adding more layers.
However, the planar profile resulting from the CMP process is often dependent on the pattern density of the underlying layer an can thus vary by more than 30-40%. This underlying pattern dependency is discussed, for example, in “An Integrated Characterization and Modeling Methodology for CMP Dielectric Planarization,” Ouma et al., Proc. of Interconnect Technology Conference, February 1998, pp. 67-69, the entirety of which is incorporated by reference herein.
One method of reducing CMP planar profile variation resulting from pattern dependency is with the use of dummy metal fills. In particular, dummy metal fills or features are inserted onto the wafer prior to the CMP process so as to make the pattern density more uniform in IC chips, i.e., to help level the feature density across the layout. Uniform feature density improves wafer-processing uniformity for certain operations such as CMP. Thus, dummy metal fills facilitate in reducing the pattern-dependent profile variation after CMP.
Placement of the dummy fills are typically made according to conventional dummy fill rules that locate the uniform-densities dummy where space is available (rule-based dummy fill). See, for example, “Analyzing the Effects of Floating Dummy-Fills: From Feature Scale Analysis to Full-Chip RC Extraction,” Lee et al., Proc. of IEDM 2001, December 2001, the entirety of which is incorporated by reference herein. However, one problem with the rule-based dummy fill is that the range of allowable dummy-filled density is relatively large such that the prescribed density is generally determined through trial-and-error for each design.
Model-based dummy filling can also be utilized to reduce CMP planar profile variation resulting from pattern dependency. Because the CMP planar profile is generally proportional to the effective pattern density as a result of an averaging effect caused by the rotation of the polishing pad, model-based dummy filling can reduce the large planar profile variation by selectively inserting dummy fills to achieve an effective density to within a predetermined range. See, for example, “Model-Based Dummy Feature Placement for Oxide Chemical-Mechanical Polishing Manufacturability,” Tian et al., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, No. 7, July 2001, pp. 902-910, the entirety of which is incorporated by reference herein.
However, the inserted dummy metal fills adversely affect the electrical field and increase the capacitance of the original metal lines. The increase in the net capacitances can be more than 25% in certain long critical nets. Some nets span across the entire chip making their effect on the performance of the chip critical. Common critical nets are global control signals such as clocks. Generally, the total delay for long interconnect nets is dominated by the interconnect RC delay such that increase in the total net delay is directly proportional to increase in the net capacitance. Thus, a 25% net delay increase can be sufficient to cause a fault condition for the circuit functionality.
As noted in Tian, referenced above, the capacitance decreases rapidly with the distance between the dummy metals and original metal lines. In order to reduce the capacitance increase, Tian proposed a model-based dummy metal fill that maximizes the distance between original metal lines and dummy metals within a cell within available area constraints. The method proposed by Tian attempts to reduce the capacitance increase for all nets. However, it is difficult to reduce the capacitance increase for all nets and the method proposed by Tian can not guarantee a reduction of the capacitance increase to within a specified range for the long timing-critical nets.
Thus, what is needed are systems and methods for improving the uniformity of planar profile after CMP while reducing the capacitance increase to within a specified range for long timing-critical nets.
SUMMARY OF THE INVENTION
Systems and methods for limiting capacitance increase due to dummy fill metals utilized to improve planar profile uniformity are disclosed. The systems and methods take into account the influence of dummy fill metals that are transferred to structures printed on the wafer to thereby limit the capacitance increase. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium such as a computer readable storage medium or a component network wherein program instructions are sent over optical or electronic communication lines. Several inventive embodiments of the present invention are described below.
A computer-automated method for locating dummy fills in an integrated circuit fabrication process generally comprises reading a layout file specifying layout of the integrated circuit, designating at least one net of the integrated circuit as a critical net, the critical nets being only a subset of all nets of the integrated circuit, identifying metal conductors corresponding to each designated critical net from the layout file, delineating a net blocking exclusion zone extending a distance of a minimum net blocking distance (NBD) from the metal conductor for each metal conductor i
Kuo Jung-hua
Ubitech, Inc.
Whitmore Stacy A.
LandOfFree
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