Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-06-17
2008-06-17
Sough, Hyung (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S144000, C711S119000, C711S147000, C711S148000, C711S117000, C711S151000, C711S156000, C711S159000, C707S793000, C707S793000, C709S201000, C709S213000, C709S217000
Reexamination Certificate
active
07389389
ABSTRACT:
A protocol engine is for use in each node of a computer system having a plurality of nodes. Each node includes an interface to a local memory subsystem that stores memory lines of information, a directory, and a memory cache. The directory includes an entry associated with a memory line of information stored in the local memory subsystem. The directory entry includes an identification field for identifying sharer nodes that potentially cache the memory line of information. The identification field has a plurality of bits at associated positions within the identification field. Each respective bit of the identification field is associated with one or more nodes. The protocol engine furthermore sets each bit in the identification field for which the memory line is cached in at least one of the associated nodes. In response to a request for exclusive ownership of a memory line, the protocol engine sends an initial invalidation request to no more than a first predefined number of the nodes associated with set bits in the identification field of the directory entry associated with the memory line.
REFERENCES:
patent: 5634110 (1997-05-01), Laudon et al.
patent: 6493809 (2002-12-01), Safranek et al.
patent: 6564302 (2003-05-01), Yagi et al.
patent: 6631447 (2003-10-01), Morioka et al.
patent: 6631448 (2003-10-01), Weber
patent: 2001/0013089 (2001-08-01), Weber
patent: 2002/0059500 (2002-05-01), McCracken et al.
Beng-Hong Lim et al., “Reactive Synchronization Algorithms for Multiprocessors,” Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operation Systems (ASPLOS VI), pp. 25-35, Oct. 1994.
Luiz A. Barroso et al., “Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing,” Copyright ACM 2000 (pp. 282-293).
Brian N. Bershad et al., “Fast Mutual Exclusion for Uniprocessors,” In Proceedings of 5th Conference on Architectural Support for Programming Languages and Operating Systems, Oct. 1992, pp. 223-233.
J. Eliot et al., “Concurrency Features for the Trellis/Owl Language,” In the proceedings of European conference on Object-Oriented Programming 1987 (ECOOP '87), Paris, France, Jun. 1987, pp. 171-180.
David A. Patterson, “Computer Architecture A Quantitative Approach,” Second Edition, Published 1990, 2nd edition 1996, pp. 679-685.
Barroso Luiz A.
Gharachorloo Kourosh
Nowatzyk Andreas
Ravishankar Mosur K.
Stets, Jr. Robert J.
Chery Mardochee
Hewlett--Packard Development Company, L.P.
Sough Hyung
LandOfFree
System and method for limited fanout daisy chaining of cache... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for limited fanout daisy chaining of cache..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for limited fanout daisy chaining of cache... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2808397