System and method for level translation in serial data...

Details System and method for level translation in serial data... System and method for level translation in serial data...

2011-05-24

2011-05-24

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S063000, C327S093000

Reexamination Certificate

active

07948270

ABSTRACT:
The serial interface operable, for example, to facilitate high speed differential data transfer between integrated circuits provides level shifting of an incoming data signal using a switched capacitor technique which level shifts the common mode voltage with minimal attenuation and minimal reduction of bandwidths. The serial interface also includes a DC offset correction loop of the input data receiver path. The level shifting circuit operates by sensing the incoming common mode voltage of a differential data signal with a resistor divider and sampling the difference between the measured input common mode voltage and desired input differential voltages generated by a differential DAC in the DC offset correction loop on two small capacitors. The small capacitors are switched across larger in-signal-path capacitors cyclically, so that over time a charge will build up to give the desired level shift to shift the common mode voltage of the incoming signal to the level tolerable by low voltage high speed transistors in the receiving integrated circuit.

REFERENCES:
patent: 6147522 (2000-11-01), Rhode et al.
patent: 6184726 (2001-02-01), Haeberli et al.
patent: 6856169 (2005-02-01), Frans et al.
patent: 7019576 (2006-03-01), Sancheti et al.
patent: 7049848 (2006-05-01), Brooks et al.
patent: 7417462 (2008-08-01), Wong et al.
patent: 7659745 (2010-02-01), Wong et al.

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