Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-11-28
2006-11-28
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07143244
ABSTRACT:
A system and method for communicating a side effect of one data request, or other event, as part of a response to another data request or event. The side effect may include notification of the invalidation of cached data, from an upstream cache to a downstream cache. The upstream cache may store invalidation notifications as they are generated or received, and as responses to data requests are sent downstream, piggyback or merge one or more notifications with a response. This scheme avoids the need to open separate communication connections using specified invalidation accounts and passwords.
REFERENCES:
patent: 6799251 (2004-09-01), Jacobs et al.
patent: 2002/0004813 (2002-01-01), Agrawal et al.
patent: 2003/0004998 (2003-01-01), Datta
patent: 2003/0046357 (2003-03-01), Doyle et al.
patent: 2004/0049579 (2004-03-01), Ims et al.
patent: 2004/0148474 (2004-07-01), Cuomo et al.
Goell Fredric
Jacobs Lawrence
Ling Shu
Liu Xiang
Doan Duc T
Oracle International Corp.
Padmanabhan Mano
Park Vaughan & Fleming LLP
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