System and method for interrupt command queuing and ordering

Details System and method for interrupt command queuing and ordering System and method for interrupt command queuing and ordering

1998-08-31

2000-05-16

Sheikh, Ayaz R.

Electrical computers and digital data processing systems: input/

Interrupt processing

Interrupt queuing

710264, G06F 1324, G06F 1326

Patent

active

060650885

ABSTRACT:
An input/output bus bridge and command queuing system includes an external interrupt router for receiving interrupt commands from bus unit controllers (BUCs) and responds with end of interrupt (EOI), interrupt return (INR) and interrupt reissue (IRR) commands. The interrupt router includes a first command queue for ordering EOI commands and a second command queue for ordering INR and IRR commands. A first in first out (FIFO) command queue orders bus memory mapped input output (MMIO) commands. The EOI commands are directed from the first command queue to the input of the FIFO command queue. The EOI commands and the MMIO commands are directed from the command queue to an input output bus and the INR and IRR commands are directed from the second command queue to the input output bus. In this way, strict ordering of EOI commands relative to MMIO accesses is maintained while simultaneously allowing INR and IRR commands to bypass enqueued MMIO accesses.

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