Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1998-04-27
2001-03-27
Ellis, Kevin L. (Department: 2751)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S167000, C712S216000
Reexamination Certificate
active
06209073
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to data processing systems, and in particular, to the execution of instructions within a microprocessor.
BACKGROUND INFORMATION
Certain processors (such as the PowerPC processor) bus serialize blocking instructions such as EIEIO (enforce in-order execution of I/O) which itself serializes storage accesses at their outgoing queues. Typically when an EIEIO instruction is executed, all storage access operations posted prior to the execution of the EIEIO instruction are marked for performance on the bus before any storage accesses that may be posted subsequent to the execution of the EIEIO instruction. Although the processor will not necessarily perform these transactions on the bus immediately, the programmer is assured that they will be performed on the bus before any subsequently posted storage accesses. In other words, the EIEIO instruction forces all EIEIO ordered storage accesses to finish on the bus before the EIEIO instruction releases to the bus. EIEIO completion on the bus allows EIEIO ordered storage accesses behind the EIEIO instruction access to the bus. In general, this can be applied to any instruction which orders some but not all subsequent instructions.
As an example of the benefit of such an instruction, assume that the programmer must write two parameter words, read a status register and then one command word to a fixed-disk controller and that the controller's ports are implemented as memory/mapped I/O ports. If the programmer executes the three stores and one load in order, the processor will post the writes but not perform them immediately. In addition, when it does acquire the external bus and performs the memory write or read transactions, it may not perform them in the same order as that specified by the programmer. This might result in improper operation of the disk controller (because it might receive the command word before the parameters and proceed to execute the command using old parameters).
To ensure that the first two stores (to write the parameter words to the disk controller) are performed prior to the store of the command word, the programmer should follow the first two stores with an EIEIO instruction. This would mark these two stores for performance on the bus prior to any subsequently posted writes. The third store (to the command register) would be executed after the EIEIO instruction and posted in the write queue. When the processor's system interface performs the three memory write transactions, the first two stores will be performed before the third one.
The problem with such typical EIEIO instructions is that they execute serially above the bus interface, as illustrated in FIG.
2
. The EIEIO instruction blocks all subsequent instructions from executing until the EIEIO completes its bus activity. As a result, cache hit loads (e.g., LD
3
) not ordered by the EIEIO instruction wait unnecessarily behind the serially executed EIEIO.
FIG. 3
provides a simple illustration of that portion of a microprocessor pertaining to storage accesses. Instructions arrive at the execution unit(s)
301
, which may require storage accesses through the load/store unit
28
, which will contain a load queue
302
and a store queue
303
. The load and store instructions are queued for transfer to the bus interface unit
12
coupled to the bus
11
, which provides access to the main memory system
39
(see FIG.
1
).
As discussed above, prior art EIEIO-type instructions block all subsequent instructions from executing at the execution stage. When the EIEIO instruction is sent down out of execution, then no other storage access type instructions, including further EIEIO instructions, can be sent to data cache
16
. Consequently, storage access instructions, which could be satisfied by access to data cache
16
and do not require the considerably longer access to main memory
39
, are also blocked by the EIEIO instruction at the execution stage. As an example, in
FIG. 2
, Group 1 illustrates load instructions LD
1
and LD
2
, followed by an EIEIO instruction EIEIO
1
serially programmed in three consecutive clock cycles. The typical EIEIO instruction then provides a block to subsequent storage access instructions at the execute stage. Store instructions ST
1
and ST
2
and load instructions LD
3
and LD
4
, along with the second EIEIO instruction, EIEIO
2
, are not permitted to execute until some undetermined number of clock cycles m when the instructions LD
1
and LD
2
have been fully executed and completed over the bus
11
.
In this example, load instruction LD
3
is a cacheable load that can execute and hit on data cache
16
. However, with the prior art EIEIO instruction configuration, the execution of instruction LD
3
will also have to wait the indeterminate number of clock cycles m.
As a result, there is a need in the art for an improvement over the above scenario.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing need by providing that EIEIO-type instructions block at the bus interface queues and not at the execution stage. The present invention implements the EIEIO instructions within the store queue when the store queue strongly orders storage accesses. However, the converse situation may be implemented whereby the EIEIO instructions are ordered within the load queue. The barrier function provided by the EIEIO instruction is implemented in the load queue via pointers back to locations in the store queue. The store queue by its nature automatically orders the stores with respect to the EIEIO instruction. The store queue sends a barrier valid and reference value to perform ordering in the load queue. A given load entry cannot arbitrate for the bus if the barrier valid asserts and its store reference does not equal the barrier reference value. The load queue informs the store queue that no load accesses match the barrier reference value. The “no match” loads include loads with a valid reference that do not equal the barrier reference value and loads without a valid reference. A “no match” load queue allows the store queue to run the EIEIO instruction on the bus.
An advantage of the present invention is that it allows the processor to perform additional instructions, such as cacheable load instructions.
Another advantage of the present invention is that the EIEIO instructions of the present invention order storage accesses downstream but do not block the processor from executing other instructions not ordered by the EIEIO instruction.
Yet another advantage of the present invention is that it allows additional EIEIO instructions to be executed and provide subsequent barriers ensuring ordering of multiple groups of storage instructions.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 4858116 (1989-08-01), Gillett, Jr. et al.
patent: 4941083 (1990-07-01), Gillett, Jr. et al.
patent: 5341491 (1994-08-01), Ramanujan
patent: 5465336 (1995-11-01), Imai et al.
patent: 5490261 (1996-02-01), Bean et al.
patent: 5649137 (1997-07-01), Favor et al.
patent: 5655096 (1997-08-01), Branigan
Compile-Time Elimination of Store-Fetch Interlock Delays, IBM Technical Disclosure Bulletin, vol. 37 No. 10, Oct. 1994, pp. 217-218.
Dual Load/Store Unit with a Single Port Cache, IBM Technical Disclosure Bulletin, vol. 38 No. 08, Aug. 1995, pp. 11-15.
Arnold Ronny Lee
Okpisz Alexander Edward
Petersen Thomas Albert
Tuvell Amy May
Ellis Kevin L.
England Anthony V. S.
International Business Machines Corp.
Kordzik Kelly K.
Winstead Sechrest & Minick P.C.
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