Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-11-26
2002-11-19
Beausoleil, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S030000, C714S726000, C714S727000
Reexamination Certificate
active
06484275
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to processor testing and, in particular, to a system and method for interfacing data with a test access port of a processor that captures state data of the processor to test the processor for errors in execution.
2. Related Art
Computer processors can be tested in a variety of ways to ensure that the processors are operating properly. For example, to test a processor, the data output by the processor can be analyzed for errors. If an error is detected, then a user is aware that the processor contains either a manufacturing or a design defect.
Monitoring the output data of the processor can provide useful information as to whether a problem exists but often fails to isolate or identify the source of the problem. In this regard, an error during execution may occur several hundred or thousand clock cycles before the processor outputs incorrect data. By the time the output data indicates that an error has occurred, the state of the processor has changed, and it may be difficult to determine what the state of the processor was when the error in execution occurred. Accordingly, it is often difficult to determine the cause of an error by externally analyzing the data output by the processor.
To facilitate debugging of processors, testing devices have been developed that capture the internal state of processors during execution so that errors can be better identified. In this regard, an error in execution generally affects the state of the processor when the error occurs. Therefore, by analyzing the state of the processor, an error in execution can be detected long before the error produces unreliable results in output data, and the state of the processor at the occurrence of the error in execution can be determined. Accordingly, it is easier to isolate or identify the cause of the error. In other words, it is easier to debug the processor.
However, most testing devices for capturing the state of processors are expensive and, for proper operation, require an operator knowledgeable with the operation of the testing device and the processor being tested. Furthermore, many of the processors that need to be tested have already been implemented in a system that is oftentimes remotely located. Therefore, the operator must often inconveniently travel to the site of the system so that the processor associated with the system can be tested.
Thus, a heretofore unaddressed need exists in the industry for providing a low cost system and method of efficiently and conveniently interfacing data with a test access port of a processor for testing purposes.
SUMMARY OF THE INVENTION
The present invention overcomes the inadequacies and deficiencies of the prior art as discussed hereinbefore. Generally, the present invention provides a system and method for enabling a processor to interface data with the processor's test access port.
A processor in accordance with the present invention includes memory that has test data and control data stored therein. The processor also includes a test application that transmits the test data and the control data from the processor's memory to a test access port of the processor. The test access port then utilizes the test data and the control data to capture state data that defines at least one state of the processor while the processor is executing. This state data may be analyzed via conventional techniques to detect and isolate errors in the execution of the processor.
In accordance with another feature of the present invention, the test access port is interfaced with a multiplexer. The multiplexer is also interfaced with the memory and an input interface capable of receiving external signals. Based on a control signal, the multiplexer selects signals defined by the test and control data transmitted from the memory or selects external signals transmitted from the input interface. The multiplexer then transmits the selected signals to the test access port, which captures state data based on the selected signals. As a result, the data used by the test access port to capture state data from the processor may be received from the memory or from an external device.
In accordance with another feature of the present invention, the test data and the control data are transmitted from the memory in parallel. Before the test access port receives this data, a first register converts the test data into serial form, and a second register converts the control data into serial form.
In accordance with another feature of the present invention, a clock within the processor is used to generate a clock signal that controls the timing of the signals transmitted to the test access port. The frequency of the control signal may be modified to synchronize the clock signal with the test access port.
The present invention can also be viewed as providing a method for testing processors. The method can be broadly conceptualized by the following steps: providing a processor having memory, a test access port, and a multiplexer, the test access port interfaced with the multiplexer; storing test data and control data into the memory, the control data corresponding with the test data; transmitting the test data and the control data from the memory to the multiplexer; selecting the test data and the control data at the multiplexer; transmitting the test data and the control data from the multiplexer to the test access port; receiving the test data and the control data at the test access port; utilizing the test data and the control data received by the test access port to capture state data defining at least one state of the processor; and analyzing the state data to identify errors associated with the processor.
Other features and advantages of the present invention will become apparent to one skilled in the art upon examination of the following detailed description, when read in conjunction with the accompanying drawings. It is intended that all such features and advantages be included herein within the scope of the present invention and protected by the claims.
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Dixon Daniel J
Finnell James S
Josephson Don D
Beausoleil Robert
Duncan Marc
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