System and method for inline invalidation of cached data

Details System and method for inline invalidation of cached data System and method for inline invalidation of cached data

2006-08-08

2006-08-08

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

07089363

ABSTRACT:
A system and method for communicating a side effect of a data request, from a data server and through one or more caches, inline with a response to the request. Instead of sending a separate notification of the side effect (e.g., instructions to invalidate data cached in one or more caches), the notification is included in the response. As the response traverses caches on its way to the requestor, each cache applies the side effect with the proper timing. Thus, data invalidation may be performed prior to caching data included in the request and/or forwarding the response toward the requester. A final cache configured to serve the response to the requestor may remove the side effect notification before serving the response.

REFERENCES:
patent: 2003/0004998 (2003-01-01), Datta
patent: 2003/0009563 (2003-01-01), Douglis et al.
patent: 2004/0162886 (2004-08-01), Ims et al.

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